237 lines
27 KiB
Text
237 lines
27 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1495977 # Simulator instruction rate (inst/s)
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host_mem_usage 209700 # Number of bytes of host memory used
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host_seconds 59.05 # Real time elapsed on the host
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host_tick_rate 2185213288 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 88340674 # Number of instructions simulated
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sim_seconds 0.129042 # Number of seconds simulated
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sim_ticks 129042205000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 20958.331276 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18958.331276 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 1273533000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 1152003000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 3744825000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 3445239000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 23833.613541 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 5018358000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4597242000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 23833.613541 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 21833.613541 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 34679457 # number of overall hits
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system.cpu.dcache.overall_miss_latency 5018358000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 210558 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4597242000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 200247 # number of replacements
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system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4080.920336 # Cycle average of tags in use
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system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 737102000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 147714 # number of writebacks
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system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 14131.456382 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 12131.456382 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 1080152000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 927280000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 14131.456382 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
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system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 1080152000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
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system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 927280000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 14131.456382 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 12131.456382 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 88264239 # number of overall hits
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system.cpu.icache.overall_miss_latency 1080152000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
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system.cpu.icache.overall_misses 76436 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 927280000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 74391 # number of replacements
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system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1876.903920 # Cycle average of tags in use
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system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 3158716000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 89695 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 1045132000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.346251 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 47506 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 522566000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.346251 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 47506 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 21989.380531 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 136664000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
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system.cpu.l2cache.Writeback_misses 147714 # number of Writeback misses
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system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
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system.cpu.l2cache.Writeback_mshr_misses 147714 # number of Writeback MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 2.294067 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 89695 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 4203848000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.680549 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 191084 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 2101924000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.680549 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 191084 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 89695 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 4203848000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.680549 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 191084 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 2101924000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.680549 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 191084 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.l2cache.replacements 24953 # number of replacements
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system.cpu.l2cache.sampled_refs 40841 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 4393.051484 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 93692 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 129042205000 # number of cpu cycles simulated
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system.cpu.num_insts 88340674 # Number of instructions executed
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system.cpu.num_refs 35224019 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
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---------- End Simulation Statistics ----------
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