b511128507
arch/alpha/faults.cc:
Renamed the _stat stat to a more descriptive _count, got rid of some old commented out code, and moved common fault handling code, ie recording that the fault happend and that it wasn't mispeculated, into the FaultBase class.
arch/alpha/faults.hh:
Renamed the _stat stat to the more descriptive _count, and renamed the appropriate accessor functions.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
The fault statistics are now handled by the fault classes themselves.
sim/faults.cc:
The default implementation of the "invoke" method now does what all faults should do first, ie record that the fault happened, and make sure the fault isn't being executed on a mispeculated execution path.
sim/faults.hh:
There is now a default implementation of invoke, and the stat function is taken care of in the architecture specific fault classes.
--HG--
extra : convert_revision : f6656fbea991df9addf85cad740ac37b1036b71a
135 lines
4.4 KiB
C++
135 lines
4.4 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/alpha/faults.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/base.hh"
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#include "base/trace.hh"
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namespace AlphaISA
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{
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FaultName MachineCheckFault::_name = "mchk";
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FaultVect MachineCheckFault::_vect = 0x0401;
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FaultStat MachineCheckFault::_count;
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FaultName AlignmentFault::_name = "unalign";
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FaultVect AlignmentFault::_vect = 0x0301;
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FaultStat AlignmentFault::_count;
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FaultName ResetFault::_name = "reset";
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FaultVect ResetFault::_vect = 0x0001;
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FaultStat ResetFault::_count;
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FaultName ArithmeticFault::_name = "arith";
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FaultVect ArithmeticFault::_vect = 0x0501;
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FaultStat ArithmeticFault::_count;
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FaultName InterruptFault::_name = "interrupt";
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FaultVect InterruptFault::_vect = 0x0101;
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FaultStat InterruptFault::_count;
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FaultName NDtbMissFault::_name = "dtb_miss_single";
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FaultVect NDtbMissFault::_vect = 0x0201;
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FaultStat NDtbMissFault::_count;
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FaultName PDtbMissFault::_name = "dtb_miss_double";
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FaultVect PDtbMissFault::_vect = 0x0281;
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FaultStat PDtbMissFault::_count;
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FaultName DtbPageFault::_name = "dfault";
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FaultVect DtbPageFault::_vect = 0x0381;
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FaultStat DtbPageFault::_count;
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FaultName DtbAcvFault::_name = "dfault";
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FaultVect DtbAcvFault::_vect = 0x0381;
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FaultStat DtbAcvFault::_count;
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FaultName ItbMissFault::_name = "itbmiss";
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FaultVect ItbMissFault::_vect = 0x0181;
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FaultStat ItbMissFault::_count;
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FaultName ItbPageFault::_name = "itbmiss";
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FaultVect ItbPageFault::_vect = 0x0181;
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FaultStat ItbPageFault::_count;
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FaultName ItbAcvFault::_name = "iaccvio";
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FaultVect ItbAcvFault::_vect = 0x0081;
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FaultStat ItbAcvFault::_count;
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FaultName UnimplementedOpcodeFault::_name = "opdec";
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FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
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FaultStat UnimplementedOpcodeFault::_count;
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FaultName FloatEnableFault::_name = "fen";
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FaultVect FloatEnableFault::_vect = 0x0581;
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FaultStat FloatEnableFault::_count;
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FaultName PalFault::_name = "pal";
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FaultVect PalFault::_vect = 0x2001;
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FaultStat PalFault::_count;
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FaultName IntegerOverflowFault::_name = "intover";
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FaultVect IntegerOverflowFault::_vect = 0x0501;
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FaultStat IntegerOverflowFault::_count;
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#if FULL_SYSTEM
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void AlphaFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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countStat()++;
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// exception restart address
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if (setRestartAddress() || !xc->inPalMode())
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xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
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if (skipFaultingInstruction()) {
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// traps... skip faulting instruction.
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xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
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xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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if (!xc->inPalMode())
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AlphaISA::swap_palshadow(&(xc->regs), true);
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xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
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xc->regs.npc = xc->regs.pc + sizeof(MachInst);
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}
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void ArithmeticFault::invoke(ExecContext * xc)
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{
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FaultBase::invoke(xc);
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panic("Arithmetic traps are unimplemented!");
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}
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#endif
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} // namespace AlphaISA
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