b4b50f8230
Adjust the traffic generator time-out so that the script works out of the box Change-Id: I6b3b6b11f98b094ae3acdbe09488c26e4aeb0ab4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
306 lines
10 KiB
Python
306 lines
10 KiB
Python
# Copyright (c) 2015-2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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import gzip
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import optparse
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import os
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import m5
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from m5.objects import *
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from m5.util import addToPath
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from m5.internal.stats import periodicStatDump
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addToPath('../common')
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import MemConfig
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addToPath('../../util')
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import protolib
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# this script is helpful to observe the memory latency for various
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# levels in a cache hierarchy, and various cache and memory
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# configurations, in essence replicating the lmbench lat_mem_rd thrash
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# behaviour
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# import the packet proto definitions, and if they are not found,
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# attempt to generate them automatically
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try:
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import packet_pb2
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except:
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print "Did not find packet proto definitions, attempting to generate"
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from subprocess import call
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error = call(['protoc', '--python_out=configs/dram',
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'--proto_path=src/proto', 'src/proto/packet.proto'])
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if not error:
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print "Generated packet proto definitions"
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try:
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import google.protobuf
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except:
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print "Please install the Python protobuf module"
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exit(-1)
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import packet_pb2
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else:
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print "Failed to import packet proto definitions"
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exit(-1)
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parser = optparse.OptionParser()
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parser.add_option("--mem-type", type="choice", default="DDR3_1600_x64",
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choices=MemConfig.mem_names(),
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help = "type of memory to use")
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parser.add_option("--mem-size", action="store", type="string",
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default="16MB",
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help="Specify the memory size")
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parser.add_option("--reuse-trace", action="store_true",
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help="Prevent generation of traces and reuse existing")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# start by creating the system itself, using a multi-layer 2.0 GHz
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# crossbar, delivering 64 bytes / 3 cycles (one header cycle) which
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# amounts to 42.7 GByte/s per layer and thus per port
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system = System(membus = SystemXBar(width = 32))
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system.clk_domain = SrcClockDomain(clock = '2.0GHz',
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voltage_domain =
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VoltageDomain(voltage = '1V'))
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mem_range = AddrRange(options.mem_size)
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system.mem_ranges = [mem_range]
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# do not worry about reserving space for the backing store
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system.mmap_using_noreserve = True
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# currently not exposed as command-line options, set here for now
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options.mem_channels = 1
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options.mem_ranks = 1
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options.external_memory_system = 0
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options.tlm_memory = 0
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options.elastic_trace_en = 0
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MemConfig.config_mem(options, system)
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# there is no point slowing things down by saving any data
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for ctrl in system.mem_ctrls:
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ctrl.null = True
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# the following assumes that we are using the native DRAM
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# controller, check to be sure
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if isinstance(ctrl, m5.objects.DRAMCtrl):
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# make the DRAM refresh interval sufficiently infinite to avoid
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# latency spikes
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ctrl.tREFI = '100s'
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# use the same concept as the utilisation sweep, and print the config
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# so that we can later read it in
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cfg_file_name = os.path.join(m5.options.outdir, "lat_mem_rd.cfg")
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cfg_file = open(cfg_file_name, 'w')
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# set an appropriate burst length in bytes
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burst_size = 64
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system.cache_line_size = burst_size
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# lazy version to check if an integer is a power of two
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def is_pow2(num):
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return num != 0 and ((num & (num - 1)) == 0)
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# assume we start every range at 0
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max_range = int(mem_range.end)
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# start at a size of 4 kByte, and go up till we hit the max, increase
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# the step every time we hit a power of two
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min_range = 4096
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ranges = [min_range]
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step = 1024
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while ranges[-1] < max_range:
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new_range = ranges[-1] + step
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if is_pow2(new_range):
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step *= 2
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ranges.append(new_range)
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# how many times to repeat the measurement for each data point
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iterations = 2
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# 150 ns in ticks, this is choosen to be high enough that transactions
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# do not pile up in the system, adjust if needed
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itt = 150 * 1000
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# for every data point, we create a trace containing a random address
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# sequence, so that we can play back the same sequence for warming and
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# the actual measurement
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def create_trace(filename, max_addr, burst_size, itt):
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try:
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proto_out = gzip.open(filename, 'wb')
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except IOError:
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print "Failed to open ", filename, " for writing"
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exit(-1)
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# write the magic number in 4-byte Little Endian, similar to what
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# is done in src/proto/protoio.cc
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proto_out.write("gem5")
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# add the packet header
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header = packet_pb2.PacketHeader()
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header.obj_id = "lat_mem_rd for range 0:" + str(max_addr)
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# assume the default tick rate (1 ps)
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header.tick_freq = 1000000000000
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protolib.encodeMessage(proto_out, header)
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# create a list of every single address to touch
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addrs = range(0, max_addr, burst_size)
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import random
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random.shuffle(addrs)
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tick = 0
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# create a packet we can re-use for all the addresses
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packet = packet_pb2.Packet()
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# ReadReq is 1 in src/mem/packet.hh Command enum
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packet.cmd = 1
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packet.size = int(burst_size)
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for addr in addrs:
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packet.tick = long(tick)
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packet.addr = long(addr)
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protolib.encodeMessage(proto_out, packet)
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tick = tick + itt
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proto_out.close()
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# this will take a while, so keep the user informed
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print "Generating traces, please wait..."
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nxt_range = 0
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nxt_state = 0
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period = long(itt * (max_range / burst_size))
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# now we create the states for each range
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for r in ranges:
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filename = os.path.join(m5.options.outdir,
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'lat_mem_rd%d.trc.gz' % nxt_range)
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if not options.reuse_trace:
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# create the actual random trace for this range
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create_trace(filename, r, burst_size, itt)
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# the warming state
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cfg_file.write("STATE %d %d TRACE %s 0\n" %
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(nxt_state, period, filename))
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nxt_state = nxt_state + 1
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# the measuring states
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for i in range(iterations):
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cfg_file.write("STATE %d %d TRACE %s 0\n" %
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(nxt_state, period, filename))
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nxt_state = nxt_state + 1
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nxt_range = nxt_range + 1
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cfg_file.write("INIT 0\n")
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# go through the states one by one
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for state in range(1, nxt_state):
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cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
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cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
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cfg_file.close()
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# create a traffic generator, and point it to the file we just created
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system.tgen = TrafficGen(config_file = cfg_file_name,
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progress_check = '10s')
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# add a communication monitor
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system.monitor = CommMonitor()
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# connect the traffic generator to the system
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system.tgen.port = system.monitor.slave
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# create the actual cache hierarchy, for now just go with something
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# basic to explore some of the options
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from Caches import *
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# a starting point for an L3 cache
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class L3Cache(Cache):
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assoc = 16
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hit_latency = 40
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response_latency = 40
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mshrs = 32
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tgts_per_mshr = 12
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write_buffers = 16
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# note that everything is in the same clock domain, 2.0 GHz as
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# specified above
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system.l1cache = L1_DCache(size = '64kB')
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system.monitor.master = system.l1cache.cpu_side
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system.l2cache = L2Cache(size = '512kB', writeback_clean = True)
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system.l2cache.xbar = L2XBar()
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system.l1cache.mem_side = system.l2cache.xbar.slave
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system.l2cache.cpu_side = system.l2cache.xbar.master
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# make the L3 mostly exclusive, and correspondingly ensure that the L2
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# writes back also clean lines to the L3
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system.l3cache = L3Cache(size = '4MB', clusivity = 'mostly_excl')
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system.l3cache.xbar = L2XBar()
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system.l2cache.mem_side = system.l3cache.xbar.slave
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system.l3cache.cpu_side = system.l3cache.xbar.master
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system.l3cache.mem_side = system.membus.slave
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# connect the system port even if it is not used in this example
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system.system_port = system.membus.slave
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# every period, dump and reset all stats
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periodicStatDump(period)
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# run Forrest, run!
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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m5.instantiate()
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m5.simulate(nxt_state * period)
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# print all we need to make sense of the stats output
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print "lat_mem_rd with %d iterations, ranges:" % iterations
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for r in ranges:
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print r
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