6563ec8634
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
127 lines
4.3 KiB
Python
127 lines
4.3 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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# Get paths we might need
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/topologies')
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import Ruby
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import Options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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# Add the ruby specific and protocol specific options
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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options.ports=32
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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# ruby does not support atomic, functional, or uncacheable accesses
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cpus = [ MemTest(percent_functional=50,
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percent_uncacheable=0, suppress_func_warnings=True) \
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for i in xrange(nb_cores) ]
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# overwrite options.num_cpus with the nb_cores value
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options.num_cpus = nb_cores
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# system simulated
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system = System(cpu = cpus)
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# Dummy voltage domain for all our clock domains
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system.voltage_domain = VoltageDomain()
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system.clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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# Create a seperate clock domain for components that should run at
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# CPUs frequency
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system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
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voltage_domain = system.voltage_domain)
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# All cpus are associated with cpu_clk_domain
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for cpu in cpus:
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cpu.clk_domain = system.cpu_clk_domain
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system.mem_ranges = AddrRange('256MB')
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Ruby.create_system(options, False, system)
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# Create a separate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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assert(len(cpus) == len(system.ruby._cpu_ports))
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for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
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#
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# Tie the cpu port to the ruby cpu ports and
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# physmem, respectively
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#
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cpus[i].port = ruby_port.slave
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#
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# Since the memtester is incredibly bursty, increase the deadlock
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# threshold to 1 million cycles
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#
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ruby_port.deadlock_threshold = 1000000
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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