gem5/src/cpu/simple/TimingSimpleCPU.py
Andreas Hansson b3f930c884 CPU: Moving towards a more general port across CPU models
This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
2012-01-17 12:55:08 -06:00

34 lines
1.7 KiB
Python

# Copyright (c) 2007 The Regents of The University of Michigan
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# Authors: Nathan Binkert
from m5.params import *
from BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'