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gem5/src/mem
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Nilay Vaish b3db882dee ruby: remove the three files related to profiling 
This patch removes the following three files: RubySlicc_Profiler.sm,
RubySlicc_Profiler_interface.cc and RubySlicc_Profiler_interface.hh.
Only one function prototyped in the file RubySlicc_Profiler.sm. Rest of the
code appearing in any of these files is not in use. Therefore, these files
are being removed.

That one single function, profileMsgDelay(), is being moved to the protocol
files where it is in use. If we need any of these deleted functions, I think
the right way to make them visible is to have the AbstractController class in
a .sm and let the controller state machine inherit from this class. The
AbstractController class can then have the prototypes of these profiling
functions in its definition.
2013-06-24 08:59:08 -05:00
..
cache mem: Spring cleaning of MSHR and MSHRQueue 2013-05-30 12:54:11 -04:00
config mem: Remove the IIC replacement policy 2013-01-07 13:05:39 -05:00
protocol ruby: remove the three files related to profiling 2013-06-24 08:59:08 -05:00
ruby ruby: remove the three files related to profiling 2013-06-24 08:59:08 -05:00
slicc ruby: fix slicc compiler to complain about duplicate symbols 2013-06-18 16:58:52 -05:00
abstract_mem.cc mem: Adding verbose debug output in the memory system 2013-04-22 13:20:33 -04:00
abstract_mem.hh mem: Avoid explicitly zeroing the memory backing store 2013-05-30 12:53:54 -04:00
AbstractMemory.py mem: Avoid explicitly zeroing the memory backing store 2013-05-30 12:53:54 -04:00
addr_mapper.cc mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
addr_mapper.hh mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
AddrMapper.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
bridge.cc sim: separate nextCycle() and clockEdge() in clockedObjects 2013-04-22 13:20:31 -04:00
bridge.hh mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
Bridge.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
bus.cc mem: Make returning snoop responses occupy response layer 2013-05-30 12:54:02 -04:00
bus.hh mem: Make the buses multi layered 2013-05-30 12:54:01 -04:00
Bus.py sim: Add a system-global option to bypass caches 2013-02-15 17:40:09 -05:00
coherent_bus.cc mem: Make returning snoop responses occupy response layer 2013-05-30 12:54:02 -04:00
coherent_bus.hh mem: Make returning snoop responses occupy response layer 2013-05-30 12:54:02 -04:00
comm_monitor.cc mem: Add optional request flags to the packet trace 2013-03-26 14:46:44 -04:00
comm_monitor.hh mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
CommMonitor.py mem: Add tracing support in the communication monitor 2013-01-07 13:05:37 -05:00
fs_translating_port_proxy.cc mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
mem_object.hh Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
MemObject.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
noncoherent_bus.cc mem: Make the buses multi layered 2013-05-30 12:54:01 -04:00
noncoherent_bus.hh mem: Make the buses multi layered 2013-05-30 12:54:01 -04:00
packet.cc mem: Adding verbose debug output in the memory system 2013-04-22 13:20:33 -04:00
packet.hh mem: Adding verbose debug output in the memory system 2013-04-22 13:20:33 -04:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc mem: Adding verbose debug output in the memory system 2013-04-22 13:20:33 -04:00
packet_queue.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
page_table.cc sim: Fix two bugs relating to software caching of PageTable entries. 2013-04-23 09:47:52 -04:00
page_table.hh sim: Fix two bugs relating to software caching of PageTable entries. 2013-04-23 09:47:52 -04:00
physical.cc mem: Avoid explicitly zeroing the memory backing store 2013-05-30 12:53:54 -04:00
physical.hh mem: Merge ranges that are part of the conf table 2013-01-07 13:05:38 -05:00
port.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
port.hh mem: Make returning snoop responses occupy response layer 2013-05-30 12:54:02 -04:00
port_proxy.cc MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
request.hh kvm: Use the address finalization code in the TLB 2013-06-18 16:10:22 +02:00
SConscript mem: Add tracing support in the communication monitor 2013-01-07 13:05:37 -05:00
se_translating_port_proxy.cc SETranslatingPortProxy: fix bug in tryReadString() 2012-08-06 16:57:11 -07:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
simple_dram.cc mem: Add bytes per activate DRAM controller stat 2013-05-30 12:54:13 -04:00
simple_dram.hh mem: Add bytes per activate DRAM controller stat 2013-05-30 12:54:13 -04:00
simple_mem.cc mem: Enforce strict use of busFirst- and busLastWordTime 2013-02-19 05:56:06 -05:00
simple_mem.hh mem: fix use after free issue in memories until 4-phase work complete. 2012-11-02 11:50:16 -05:00
SimpleDRAM.py mem: More descriptive DRAM config names 2013-05-30 12:54:14 -04:00
SimpleMemory.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
tport.cc mem: Replace check with panic where inhibited should not happen 2013-04-22 13:20:33 -04:00
tport.hh Port: Hide the queue implementation in SimpleTimingPort 2012-07-09 12:35:42 -04:00