5a15909bac
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
1309 lines
155 KiB
Text
1309 lines
155 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.615733 # Number of seconds simulated
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sim_ticks 2615733285000 # Number of ticks simulated
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final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 250012 # Simulator instruction rate (inst/s)
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host_op_rate 318151 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 10863402189 # Simulator tick rate (ticks/s)
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host_mem_usage 396412 # Number of bytes of host memory used
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host_seconds 240.78 # Real time elapsed on the host
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sim_insts 60198861 # Number of instructions simulated
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sim_ops 76605713 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory
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system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15494770 # Total number of read requests seen
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system.physmem.writeReqs 811989 # Total number of write requests seen
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system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 991665280 # Total number of bytes read from memory
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system.physmem.bytesWritten 51967296 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2615728912000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 6652 # Categorize read packet sizes
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system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 152694 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 754018 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 57971 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation
|
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system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20096-20159 1 0.00% 60.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20288-20351 1 0.00% 60.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22016-22079 1 0.00% 60.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22272-22335 2 0.01% 60.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22400-22463 1 0.00% 60.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::22528-22591 3 0.01% 60.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23040-23103 2 0.01% 60.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23424-23487 1 0.00% 60.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23552-23615 2 0.01% 60.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24576-24639 2 0.01% 60.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::24832-24895 2 0.01% 60.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25088-25151 2 0.01% 60.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25216-25279 1 0.00% 60.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25344-25407 2 0.01% 60.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25664-25727 1 0.00% 60.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::25792-25855 1 0.00% 60.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26112-26175 1 0.00% 60.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26240-26303 1 0.00% 60.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26368-26431 2 0.01% 60.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27392-27455 1 0.00% 60.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::27648-27711 3 0.01% 60.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::28928-28991 2 0.01% 60.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29184-29247 1 0.00% 60.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29312-29375 1 0.00% 60.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29632-29695 1 0.00% 60.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::29696-29759 2 0.01% 60.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30272-30335 1 0.00% 60.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30720-30783 4 0.01% 60.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::30848-30911 1 0.00% 60.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31424-31487 1 0.00% 60.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::31744-31807 3 0.01% 60.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33088-33151 1 0.00% 60.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33152-33215 24 0.06% 60.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33280-33343 16 0.04% 60.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::35072-35135 1 0.00% 60.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39168-39231 1 0.00% 60.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::39424-39487 1 0.00% 60.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40704-40767 1 0.00% 60.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::40960-41023 1 0.00% 60.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::41984-42047 2 0.01% 60.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42496-42559 1 0.00% 60.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::42752-42815 1 0.00% 60.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44032-44095 1 0.00% 60.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::44992-45055 1 0.00% 60.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47104-47167 2 0.01% 60.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::47616-47679 1 0.00% 60.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::95680-95743 1 0.00% 99.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::96064-96127 1 0.00% 99.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::98880-98943 1 0.00% 99.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::103488-103551 1 0.00% 99.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::117184-117247 1 0.00% 99.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::118272-118335 1 0.00% 99.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::120000-120063 1 0.00% 99.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::121792-121855 1 0.00% 99.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::124608-124671 1 0.00% 99.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation
|
|
system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 77472355000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 16272657500 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 19568.21 # Average queueing delay per request
|
|
system.physmem.avgBankLat 1050.22 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 25618.44 # Average memory access latency
|
|
system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 3.12 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.15 # Average read queue length over time
|
|
system.physmem.avgWrQLen 10.84 # Average write queue length over time
|
|
system.physmem.readRowHits 15469547 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 798405 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 160407.65 # Average gap between requests
|
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
|
system.membus.throughput 54136540 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 16546595 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 16546595 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 763368 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 763368 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 57971 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 132250 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 132250 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 141606749 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.iobus.throughput 47815955 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 8166 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 125073785 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 14996132 # DTB read hits
|
|
system.cpu.dtb.read_misses 7340 # DTB read misses
|
|
system.cpu.dtb.write_hits 11230462 # DTB write hits
|
|
system.cpu.dtb.write_misses 2218 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 15003472 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 11232680 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 26226594 # DTB hits
|
|
system.cpu.dtb.misses 9558 # DTB misses
|
|
system.cpu.dtb.accesses 26236152 # DTB accesses
|
|
system.cpu.itb.inst_hits 61492700 # ITB inst hits
|
|
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 61497171 # ITB inst accesses
|
|
system.cpu.itb.hits 61492700 # DTB hits
|
|
system.cpu.itb.misses 4471 # DTB misses
|
|
system.cpu.itb.accesses 61497171 # DTB accesses
|
|
system.cpu.numCycles 5231466570 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 60198861 # Number of instructions committed
|
|
system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
|
system.cpu.num_func_calls 2140458 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 68872503 # number of integer instructions
|
|
system.cpu.num_fp_insts 10269 # number of float instructions
|
|
system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 27394052 # number of memory refs
|
|
system.cpu.num_load_insts 15660178 # Number of load instructions
|
|
system.cpu.num_store_insts 11733874 # Number of store instructions
|
|
system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.875848 # Percentage of idle cycles
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
|
|
system.cpu.icache.tags.replacements 856294 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.881133 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 60635894 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 856806 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 70.769689 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 19815360250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.881133 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997815 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 60635894 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 60635894 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 60635894 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 60635894 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 60635894 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 60635894 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 856806 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 856806 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 856806 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 856806 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 856806 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 856806 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768628750 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11768628750 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11768628750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11768628750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11768628750 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11768628750 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 61492700 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 61492700 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 61492700 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 61492700 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 61492700 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 61492700 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.464913 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13735.464913 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13735.464913 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13735.464913 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856806 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 856806 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 856806 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 856806 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 856806 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 856806 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049829250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10049829250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049829250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 10049829250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049829250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 10049829250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 430705250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 430705250 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11729.410450 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11729.410450 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 62586 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 50732.763816 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1683068 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 127970 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 13.152051 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 2564920911000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 37695.858347 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884553 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6997.437473 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6035.582751 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.575193 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106772 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092096 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.774121 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 844565 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 370151 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1226971 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 595786 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 595786 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
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|
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|
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|
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|
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|
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|
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|
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|
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system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency
|
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 65156.719432 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
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|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
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|
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system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702868810 # number of WriteReq MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339357750 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183699499310 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses
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|
|
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|
|
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|
|
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|
|
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|
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|
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51787.271500 # average ReadExReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency
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|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 626803 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.877792 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 23655579 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 627315 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 37.709251 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 657281250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.877792 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999761 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13195771 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13195771 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 9972807 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 9972807 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 23168578 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 23168578 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 23168578 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 23168578 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 368488 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 368488 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 250225 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 250225 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 618713 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 618713 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 618713 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 618713 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5386574000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5386574000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10624198015 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 10624198015 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 159892750 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 159892750 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 16010772015 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 16010772015 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 595786 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 368488 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250225 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 250225 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 618713 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 14703968485 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14703968485 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 14703968485 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234980190 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234980190 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|