gem5/python/m5
Ali Saidi b38f67d5b7 Implement a very very simple bus
requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-25 18:31:20 -05:00
..
objects Implement a very very simple bus 2006-03-25 18:31:20 -05:00
__init__.py Regression tests now run under scons! 2005-09-05 16:31:27 -04:00
config.py Actually, you should'nt do math on Clock in the config files. 2005-11-21 00:22:29 -05:00
convert.py Allow math on CheckedInt-derived ParamValue classes w/o 2005-11-01 14:11:54 -05:00
multidict.py Add licenses in python dir. 2005-06-05 01:57:57 -04:00
smartdict.py Add licenses in python dir. 2005-06-05 01:57:57 -04:00