b38f67d5b7
requestTime -> time
responseTime -> packet.time
Make CPU and memory able to connect to the bus
dev/io_device.cc:
update for request and packet both having a time
hand platform off to port for eventual selection of request modes
dev/io_device.hh:
update for request and packet both havig a time
hand platform off to port for eventual selection of request modes
mem/bus.hh:
Add a device map struct that maps a range to a portId
- Which needs work it theory it should be an interval tree
- but it is a list and works fine right now
Add a function called findPort which returns port for an addr range
Add a deviceBlockSize function that really shouldn't exist, but it
was easier than fixing the translating port
mem/packet.hh:
add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
remove requestTime/responseTime for just time in request which
is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
Fix for new bus object
--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
140 lines
4 KiB
C++
140 lines
4 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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*/
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#ifndef __PHYSICAL_MEMORY_HH__
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#define __PHYSICAL_MEMORY_HH__
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#include "base/range.hh"
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "sim/eventq.hh"
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#include <map>
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#include <string>
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//
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// Functional model for a contiguous block of physical memory. (i.e. RAM)
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//
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class PhysicalMemory : public MemObject
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{
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class MemoryPort : public Port
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{
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PhysicalMemory *memory;
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public:
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MemoryPort(PhysicalMemory *_memory);
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protected:
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virtual bool recvTiming(Packet &pkt);
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virtual Tick recvAtomic(Packet &pkt);
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virtual void recvFunctional(Packet &pkt);
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virtual void recvStatusChange(Status status);
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virtual void getDeviceAddressRanges(AddrRangeList &range_list,
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bool &owner);
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virtual int deviceBlockSize();
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};
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MemoryPort memPort;
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virtual Port * getPort(const char *if_name);
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int numPorts;
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int lat;
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struct MemResponseEvent : public Event
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{
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Packet &pkt;
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MemoryPort *memoryPort;
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MemResponseEvent(Packet &pkt, MemoryPort *memoryPort);
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void process();
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const char *description();
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};
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private:
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// prevent copying of a MainMemory object
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PhysicalMemory(const PhysicalMemory &specmem);
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const PhysicalMemory &operator=(const PhysicalMemory &specmem);
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protected:
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Addr base_addr;
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Addr pmem_size;
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uint8_t *pmem_addr;
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int page_ptr;
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public:
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Addr new_page();
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uint64_t size() { return pmem_size; }
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public:
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PhysicalMemory(const std::string &n, MemObject *bus);
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virtual ~PhysicalMemory();
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public:
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int deviceBlockSize();
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void getAddressRanges(AddrRangeList &rangeList, bool &owner);
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void virtual init() { memPort.sendStatusChange(Port::RangeChange); }
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// fast back-door memory access for vtophys(), remote gdb, etc.
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// uint64_t phys_read_qword(Addr addr) const;
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private:
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bool doTimingAccess(Packet &pkt, MemoryPort *memoryPort);
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Tick doAtomicAccess(Packet &pkt);
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void doFunctionalAccess(Packet &pkt);
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void recvStatusChange(Port::Status status);
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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/*uint64_t
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PhysicalMemory::phys_read_qword(Addr addr) const
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{
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if (addr + sizeof(uint64_t) > pmem_size)
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return 0;
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return *(uint64_t *)(pmem_addr + addr);
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}*/
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#endif //__PHYSICAL_MEMORY_HH__
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