gem5/dev/io_device.cc
Ali Saidi b38f67d5b7 Implement a very very simple bus
requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-25 18:31:20 -05:00

204 lines
5 KiB
C++

/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "dev/io_device.hh"
#include "sim/builder.hh"
PioPort::PioPort(PioDevice *dev, Platform *p)
: device(dev), platform(p)
{ }
Tick
PioPort::recvAtomic(Packet &pkt)
{
return device->recvAtomic(pkt);
}
void
PioPort::recvFunctional(Packet &pkt)
{
device->recvAtomic(pkt);
}
void
PioPort::getDeviceAddressRanges(AddrRangeList &range_list, bool &owner)
{
device->addressRanges(range_list, owner);
}
Packet *
PioPort::recvRetry()
{
Packet* pkt = transmitList.front();
transmitList.pop_front();
return pkt;
}
void
PioPort::SendEvent::process()
{
if (port->Port::sendTiming(packet) == Success)
return;
port->transmitList.push_back(&packet);
}
PioDevice::PioDevice(const std::string &name, Platform *p)
: SimObject(name), platform(p)
{
pioPort = new PioPort(this, p);
}
bool
PioPort::recvTiming(Packet &pkt)
{
device->recvAtomic(pkt);
sendTiming(pkt, pkt.time-pkt.req->time);
return Success;
}
PioDevice::~PioDevice()
{
if (pioPort)
delete pioPort;
}
DmaPort::DmaPort(DmaDevice *dev)
: device(dev)
{ }
bool
DmaPort::recvTiming(Packet &pkt)
{
completionEvent->schedule(curTick+1);
completionEvent = NULL;
return Success;
}
DmaDevice::DmaDevice(const std::string &name, Platform *p)
: PioDevice(name, p)
{
dmaPort = new DmaPort(this);
}
void
DmaPort::SendEvent::process()
{
if (port->Port::sendTiming(packet) == Success)
return;
port->transmitList.push_back(&packet);
}
Packet *
DmaPort::recvRetry()
{
Packet* pkt = transmitList.front();
transmitList.pop_front();
return pkt;
}
void
DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
Event *event, uint8_t *data)
{
assert(event);
int prevSize = 0;
Packet basePkt;
Request baseReq;
basePkt.flags = 0;
basePkt.coherence = NULL;
basePkt.senderState = NULL;
basePkt.src = 0;
basePkt.dest = 0;
basePkt.cmd = cmd;
basePkt.result = Unknown;
basePkt.req = NULL;
baseReq.nicReq = true;
baseReq.time = curTick;
completionEvent = event;
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
Packet *pkt = new Packet(basePkt);
Request *req = new Request(baseReq);
pkt->addr = gen.addr();
pkt->size = gen.size();
pkt->req = req;
pkt->req->paddr = pkt->addr;
pkt->req->size = pkt->size;
// Increment the data pointer on a write
pkt->data = data ? data + prevSize : NULL ;
prevSize += pkt->size;
sendDma(*pkt);
}
}
void
DmaPort::sendDma(Packet &pkt)
{
// some kind of selction between access methods
// more work is going to have to be done to make
// switching actually work
/* MemState state = device->platform->system->memState;
if (state == Timing) {
if (sendTiming(pkt) == Failure)
transmitList.push_back(&packet);
} else if (state == Atomic) {*/
sendAtomic(pkt);
completionEvent->schedule(pkt.time - pkt.req->time);
completionEvent = NULL;
/* } else if (state == Functional) {
sendFunctional(pkt);
// Is this correct???
completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime);
completionEvent == NULL;
} else
panic("Unknown memory command state.");
*/
}
DmaDevice::~DmaDevice()
{
if (dmaPort)
delete dmaPort;
}