396600de10
For example if DRAM is at two locations and mirrored this patch allows the mirroring to occur.
99 lines
3.3 KiB
Python
99 lines
3.3 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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SimObject('AddrMapper.py')
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SimObject('Bridge.py')
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SimObject('Bus.py')
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SimObject('CommMonitor.py')
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SimObject('MemObject.py')
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Source('addr_mapper.cc')
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Source('bridge.cc')
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Source('bus.cc')
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Source('coherent_bus.cc')
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Source('comm_monitor.cc')
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Source('mem_object.cc')
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Source('mport.cc')
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Source('noncoherent_bus.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('packet_queue.cc')
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Source('tport.cc')
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Source('port_proxy.cc')
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Source('fs_translating_port_proxy.cc')
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Source('se_translating_port_proxy.cc')
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if env['TARGET_ISA'] != 'no':
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SimObject('AbstractMemory.py')
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SimObject('SimpleMemory.py')
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SimObject('SimpleDRAM.py')
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Source('abstract_mem.cc')
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Source('simple_mem.cc')
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Source('page_table.cc')
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Source('physical.cc')
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Source('simple_dram.cc')
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DebugFlag('BaseBus')
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DebugFlag('BusAddrRanges')
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DebugFlag('CoherentBus')
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DebugFlag('NoncoherentBus')
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CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
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'NoncoherentBus'])
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DebugFlag('Bridge')
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DebugFlag('CommMonitor')
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DebugFlag('DRAM')
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DebugFlag('DRAMWR')
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DebugFlag('LLSC')
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DebugFlag('MMU')
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DebugFlag('MemoryAccess')
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DebugFlag('PacketQueue')
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DebugFlag('ProtocolTrace')
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DebugFlag('RubyCache')
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DebugFlag('RubyCacheTrace')
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DebugFlag('RubyDma')
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DebugFlag('RubyGenerated')
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DebugFlag('RubyMemory')
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DebugFlag('RubyNetwork')
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DebugFlag('RubyPort')
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DebugFlag('RubyQueue')
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DebugFlag('RubySequencer')
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DebugFlag('RubySlicc')
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DebugFlag('RubySystem')
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DebugFlag('RubyTester')
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DebugFlag('RubyStats')
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DebugFlag('RubyResourceStalls')
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CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
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'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
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'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace'])
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