c60db56741
This patch removes the NACK frrom the packet as there is no longer any module in the system that issues them (the bridge was the only one and the previous patch removes that). The handling of NACKs was mostly avoided throughout the code base, by using e.g. panic or assert false, but in a few locations the NACKs were actually dealt with (although NACKs never occured in any of the regressions). Most notably, the DMA port will now never receive a NACK and the backoff time is thus never changed. As a consequence, the entire backoff mechanism (similar to a PCI bus) is now removed and the DMA port entirely relies on the bus performing the arbitration and issuing a retry when appropriate. This is more in line with e.g. PCIe. Surprisingly, this patch has no impact on any of the regressions. As mentioned in the patch that removes the NACK from the bridge, a follow-up patch should change the request and response buffer size for at least one regression to also verify that the system behaves as expected when the bridge fills up.
783 lines
23 KiB
C++
783 lines
23 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's I/O AT DMA copy engine.
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*/
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#include <algorithm>
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#include "base/cp_annotate.hh"
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#include "base/trace.hh"
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#include "debug/DMACopyEngine.hh"
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#include "debug/Drain.hh"
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#include "dev/copy_engine.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/CopyEngine.hh"
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#include "sim/stats.hh"
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#include "sim/system.hh"
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using namespace CopyEngineReg;
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CopyEngine::CopyEngine(const Params *p)
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: PciDev(p)
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{
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// All Reg regs are initialized to 0 by default
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regs.chanCount = p->ChanCnt;
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regs.xferCap = findMsbSet(p->XferCap);
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regs.attnStatus = 0;
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if (regs.chanCount > 64)
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fatal("CopyEngine interface doesn't support more than 64 DMA engines\n");
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for (int x = 0; x < regs.chanCount; x++) {
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CopyEngineChannel *ch = new CopyEngineChannel(this, x);
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chan.push_back(ch);
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}
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}
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CopyEngine::CopyEngineChannel::CopyEngineChannel(CopyEngine *_ce, int cid)
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: cePort(_ce, _ce->sys),
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ce(_ce), channelId(cid), busy(false), underReset(false),
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refreshNext(false), latBeforeBegin(ce->params()->latBeforeBegin),
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latAfterCompletion(ce->params()->latAfterCompletion),
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completionDataReg(0), nextState(Idle), drainEvent(NULL),
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fetchCompleteEvent(this), addrCompleteEvent(this),
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readCompleteEvent(this), writeCompleteEvent(this),
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statusCompleteEvent(this)
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{
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cr.status.dma_transfer_status(3);
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cr.descChainAddr = 0;
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cr.completionAddr = 0;
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curDmaDesc = new DmaDesc;
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memset(curDmaDesc, 0, sizeof(DmaDesc));
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copyBuffer = new uint8_t[ce->params()->XferCap];
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}
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CopyEngine::~CopyEngine()
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{
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for (int x = 0; x < chan.size(); x++) {
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delete chan[x];
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}
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}
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CopyEngine::CopyEngineChannel::~CopyEngineChannel()
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{
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delete curDmaDesc;
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delete [] copyBuffer;
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}
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MasterPort &
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CopyEngine::getMasterPort(const std::string &if_name, int idx)
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{
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if (if_name != "dma") {
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// pass it along to our super class
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return PciDev::getMasterPort(if_name, idx);
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} else {
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if (idx >= static_cast<int>(chan.size())) {
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panic("CopyEngine::getMasterPort: unknown index %d\n", idx);
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}
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return chan[idx]->getMasterPort();
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}
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}
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MasterPort &
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CopyEngine::CopyEngineChannel::getMasterPort()
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{
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return cePort;
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}
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void
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CopyEngine::CopyEngineChannel::recvCommand()
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{
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if (cr.command.start_dma()) {
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assert(!busy);
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cr.status.dma_transfer_status(0);
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nextState = DescriptorFetch;
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fetchAddress = cr.descChainAddr;
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if (ce->getState() == SimObject::Running)
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fetchDescriptor(cr.descChainAddr);
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} else if (cr.command.append_dma()) {
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if (!busy) {
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nextState = AddressFetch;
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if (ce->getState() == SimObject::Running)
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fetchNextAddr(lastDescriptorAddr);
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} else
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refreshNext = true;
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} else if (cr.command.reset_dma()) {
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if (busy)
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underReset = true;
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else {
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cr.status.dma_transfer_status(3);
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nextState = Idle;
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}
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} else if (cr.command.resume_dma() || cr.command.abort_dma() ||
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cr.command.suspend_dma())
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panic("Resume, Abort, and Suspend are not supported\n");
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cr.command(0);
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}
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Tick
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CopyEngine::read(PacketPtr pkt)
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{
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int bar;
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Addr daddr;
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if (!getBAR(pkt->getAddr(), bar, daddr))
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panic("Invalid PCI memory access to unmapped memory.\n");
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// Only Memory register BAR is allowed
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assert(bar == 0);
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int size = pkt->getSize();
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if (size != sizeof(uint64_t) && size != sizeof(uint32_t) &&
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size != sizeof(uint16_t) && size != sizeof(uint8_t)) {
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panic("Unknown size for MMIO access: %d\n", pkt->getSize());
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}
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DPRINTF(DMACopyEngine, "Read device register %#X size: %d\n", daddr, size);
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pkt->allocate();
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///
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/// Handle read of register here
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///
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if (daddr < 0x80) {
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switch (daddr) {
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case GEN_CHANCOUNT:
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assert(size == sizeof(regs.chanCount));
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pkt->set<uint8_t>(regs.chanCount);
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break;
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case GEN_XFERCAP:
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assert(size == sizeof(regs.xferCap));
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pkt->set<uint8_t>(regs.xferCap);
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break;
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case GEN_INTRCTRL:
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assert(size == sizeof(uint8_t));
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pkt->set<uint8_t>(regs.intrctrl());
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regs.intrctrl.master_int_enable(0);
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break;
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case GEN_ATTNSTATUS:
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assert(size == sizeof(regs.attnStatus));
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pkt->set<uint32_t>(regs.attnStatus);
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regs.attnStatus = 0;
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break;
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default:
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panic("Read request to unknown register number: %#x\n", daddr);
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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// Find which channel we're accessing
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int chanid = 0;
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daddr -= 0x80;
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while (daddr >= 0x80) {
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chanid++;
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daddr -= 0x80;
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}
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if (chanid >= regs.chanCount)
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panic("Access to channel %d (device only configured for %d channels)",
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chanid, regs.chanCount);
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///
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/// Channel registers are handled here
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///
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chan[chanid]->channelRead(pkt, daddr, size);
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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void
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CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
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{
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switch (daddr) {
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case CHAN_CONTROL:
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assert(size == sizeof(uint16_t));
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pkt->set<uint16_t>(cr.ctrl());
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cr.ctrl.in_use(1);
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break;
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case CHAN_STATUS:
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assert(size == sizeof(uint64_t));
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pkt->set<uint64_t>(cr.status() | ~busy);
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break;
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case CHAN_CHAINADDR:
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assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
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if (size == sizeof(uint64_t))
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pkt->set<uint64_t>(cr.descChainAddr);
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else
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pkt->set<uint32_t>(bits(cr.descChainAddr,0,31));
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break;
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case CHAN_CHAINADDR_HIGH:
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assert(size == sizeof(uint32_t));
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pkt->set<uint32_t>(bits(cr.descChainAddr,32,63));
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break;
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case CHAN_COMMAND:
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assert(size == sizeof(uint8_t));
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pkt->set<uint32_t>(cr.command());
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break;
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case CHAN_CMPLNADDR:
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assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
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if (size == sizeof(uint64_t))
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pkt->set<uint64_t>(cr.completionAddr);
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else
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pkt->set<uint32_t>(bits(cr.completionAddr,0,31));
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break;
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case CHAN_CMPLNADDR_HIGH:
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assert(size == sizeof(uint32_t));
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pkt->set<uint32_t>(bits(cr.completionAddr,32,63));
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break;
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case CHAN_ERROR:
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assert(size == sizeof(uint32_t));
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pkt->set<uint32_t>(cr.error());
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break;
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default:
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panic("Read request to unknown channel register number: (%d)%#x\n",
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channelId, daddr);
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}
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}
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Tick
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CopyEngine::write(PacketPtr pkt)
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{
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int bar;
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Addr daddr;
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if (!getBAR(pkt->getAddr(), bar, daddr))
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panic("Invalid PCI memory access to unmapped memory.\n");
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// Only Memory register BAR is allowed
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assert(bar == 0);
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int size = pkt->getSize();
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///
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/// Handle write of register here
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///
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if (size == sizeof(uint64_t)) {
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uint64_t val M5_VAR_USED = pkt->get<uint64_t>();
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DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
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} else if (size == sizeof(uint32_t)) {
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uint32_t val M5_VAR_USED = pkt->get<uint32_t>();
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DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
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} else if (size == sizeof(uint16_t)) {
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uint16_t val M5_VAR_USED = pkt->get<uint16_t>();
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DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
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} else if (size == sizeof(uint8_t)) {
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uint8_t val M5_VAR_USED = pkt->get<uint8_t>();
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DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
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} else {
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panic("Unknown size for MMIO access: %d\n", size);
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}
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if (daddr < 0x80) {
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switch (daddr) {
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case GEN_CHANCOUNT:
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case GEN_XFERCAP:
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case GEN_ATTNSTATUS:
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DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
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daddr);
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break;
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case GEN_INTRCTRL:
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regs.intrctrl.master_int_enable(bits(pkt->get<uint8_t>(),0,1));
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break;
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default:
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panic("Read request to unknown register number: %#x\n", daddr);
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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// Find which channel we're accessing
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int chanid = 0;
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daddr -= 0x80;
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while (daddr >= 0x80) {
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chanid++;
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daddr -= 0x80;
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}
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if (chanid >= regs.chanCount)
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panic("Access to channel %d (device only configured for %d channels)",
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chanid, regs.chanCount);
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///
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/// Channel registers are handled here
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///
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chan[chanid]->channelWrite(pkt, daddr, size);
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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void
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CopyEngine::CopyEngineChannel::channelWrite(Packet *pkt, Addr daddr, int size)
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{
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switch (daddr) {
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case CHAN_CONTROL:
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assert(size == sizeof(uint16_t));
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int old_int_disable;
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old_int_disable = cr.ctrl.interrupt_disable();
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cr.ctrl(pkt->get<uint16_t>());
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if (cr.ctrl.interrupt_disable())
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cr.ctrl.interrupt_disable(0);
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else
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cr.ctrl.interrupt_disable(old_int_disable);
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break;
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case CHAN_STATUS:
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assert(size == sizeof(uint64_t));
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DPRINTF(DMACopyEngine, "Warning, ignorning write to register %x\n",
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daddr);
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break;
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case CHAN_CHAINADDR:
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assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
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if (size == sizeof(uint64_t))
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cr.descChainAddr = pkt->get<uint64_t>();
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else
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cr.descChainAddr = (uint64_t)pkt->get<uint32_t>() |
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(cr.descChainAddr & ~mask(32));
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DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
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break;
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case CHAN_CHAINADDR_HIGH:
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assert(size == sizeof(uint32_t));
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cr.descChainAddr = ((uint64_t)pkt->get<uint32_t>() <<32) |
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(cr.descChainAddr & mask(32));
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DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
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break;
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case CHAN_COMMAND:
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assert(size == sizeof(uint8_t));
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cr.command(pkt->get<uint8_t>());
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recvCommand();
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break;
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case CHAN_CMPLNADDR:
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assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
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if (size == sizeof(uint64_t))
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cr.completionAddr = pkt->get<uint64_t>();
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else
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cr.completionAddr = pkt->get<uint32_t>() |
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(cr.completionAddr & ~mask(32));
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break;
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case CHAN_CMPLNADDR_HIGH:
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assert(size == sizeof(uint32_t));
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cr.completionAddr = ((uint64_t)pkt->get<uint32_t>() <<32) |
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(cr.completionAddr & mask(32));
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break;
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case CHAN_ERROR:
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assert(size == sizeof(uint32_t));
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cr.error(~pkt->get<uint32_t>() & cr.error());
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break;
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default:
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panic("Read request to unknown channel register number: (%d)%#x\n",
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channelId, daddr);
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}
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}
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void
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CopyEngine::regStats()
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{
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using namespace Stats;
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bytesCopied
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.init(regs.chanCount)
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.name(name() + ".bytes_copied")
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.desc("Number of bytes copied by each engine")
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.flags(total)
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;
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copiesProcessed
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.init(regs.chanCount)
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.name(name() + ".copies_processed")
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.desc("Number of copies processed by each engine")
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.flags(total)
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;
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}
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void
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CopyEngine::CopyEngineChannel::fetchDescriptor(Addr address)
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{
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anDq();
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anBegin("FetchDescriptor");
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DPRINTF(DMACopyEngine, "Reading descriptor from at memory location %#x(%#x)\n",
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address, ce->platform->pciToDma(address));
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assert(address);
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busy = true;
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DPRINTF(DMACopyEngine, "dmaAction: %#x, %d bytes, to addr %#x\n",
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ce->platform->pciToDma(address), sizeof(DmaDesc), curDmaDesc);
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cePort.dmaAction(MemCmd::ReadReq, ce->platform->pciToDma(address),
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sizeof(DmaDesc), &fetchCompleteEvent,
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(uint8_t*)curDmaDesc, latBeforeBegin);
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lastDescriptorAddr = address;
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}
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void
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CopyEngine::CopyEngineChannel::fetchDescComplete()
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{
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DPRINTF(DMACopyEngine, "Read of descriptor complete\n");
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if ((curDmaDesc->command & DESC_CTRL_NULL)) {
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DPRINTF(DMACopyEngine, "Got NULL descriptor, skipping\n");
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assert(!(curDmaDesc->command & DESC_CTRL_CP_STS));
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if (curDmaDesc->command & DESC_CTRL_CP_STS) {
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panic("Shouldn't be able to get here\n");
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nextState = CompletionWrite;
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if (inDrain()) return;
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writeCompletionStatus();
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} else {
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anBegin("Idle");
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anWait();
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busy = false;
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nextState = Idle;
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inDrain();
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}
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return;
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}
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if (curDmaDesc->command & ~DESC_CTRL_CP_STS)
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panic("Descriptor has flag other that completion status set\n");
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nextState = DMARead;
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if (inDrain()) return;
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readCopyBytes();
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}
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void
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CopyEngine::CopyEngineChannel::readCopyBytes()
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{
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anBegin("ReadCopyBytes");
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DPRINTF(DMACopyEngine, "Reading %d bytes from buffer to memory location %#x(%#x)\n",
|
|
curDmaDesc->len, curDmaDesc->dest,
|
|
ce->platform->pciToDma(curDmaDesc->src));
|
|
cePort.dmaAction(MemCmd::ReadReq, ce->platform->pciToDma(curDmaDesc->src),
|
|
curDmaDesc->len, &readCompleteEvent, copyBuffer, 0);
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::readCopyBytesComplete()
|
|
{
|
|
DPRINTF(DMACopyEngine, "Read of bytes to copy complete\n");
|
|
|
|
nextState = DMAWrite;
|
|
if (inDrain()) return;
|
|
writeCopyBytes();
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::writeCopyBytes()
|
|
{
|
|
anBegin("WriteCopyBytes");
|
|
DPRINTF(DMACopyEngine, "Writing %d bytes from buffer to memory location %#x(%#x)\n",
|
|
curDmaDesc->len, curDmaDesc->dest,
|
|
ce->platform->pciToDma(curDmaDesc->dest));
|
|
|
|
cePort.dmaAction(MemCmd::WriteReq, ce->platform->pciToDma(curDmaDesc->dest),
|
|
curDmaDesc->len, &writeCompleteEvent, copyBuffer, 0);
|
|
|
|
ce->bytesCopied[channelId] += curDmaDesc->len;
|
|
ce->copiesProcessed[channelId]++;
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::writeCopyBytesComplete()
|
|
{
|
|
DPRINTF(DMACopyEngine, "Write of bytes to copy complete user1: %#x\n",
|
|
curDmaDesc->user1);
|
|
|
|
cr.status.compl_desc_addr(lastDescriptorAddr >> 6);
|
|
completionDataReg = cr.status() | 1;
|
|
|
|
anQ("DMAUsedDescQ", channelId, 1);
|
|
anQ("AppRecvQ", curDmaDesc->user1, curDmaDesc->len);
|
|
if (curDmaDesc->command & DESC_CTRL_CP_STS) {
|
|
nextState = CompletionWrite;
|
|
if (inDrain()) return;
|
|
writeCompletionStatus();
|
|
return;
|
|
}
|
|
|
|
continueProcessing();
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::continueProcessing()
|
|
{
|
|
busy = false;
|
|
|
|
if (underReset) {
|
|
anBegin("Reset");
|
|
anWait();
|
|
underReset = false;
|
|
refreshNext = false;
|
|
busy = false;
|
|
nextState = Idle;
|
|
return;
|
|
}
|
|
|
|
if (curDmaDesc->next) {
|
|
nextState = DescriptorFetch;
|
|
fetchAddress = curDmaDesc->next;
|
|
if (inDrain()) return;
|
|
fetchDescriptor(curDmaDesc->next);
|
|
} else if (refreshNext) {
|
|
nextState = AddressFetch;
|
|
refreshNext = false;
|
|
if (inDrain()) return;
|
|
fetchNextAddr(lastDescriptorAddr);
|
|
} else {
|
|
inDrain();
|
|
nextState = Idle;
|
|
anWait();
|
|
anBegin("Idle");
|
|
}
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::writeCompletionStatus()
|
|
{
|
|
anBegin("WriteCompletionStatus");
|
|
DPRINTF(DMACopyEngine, "Writing completion status %#x to address %#x(%#x)\n",
|
|
completionDataReg, cr.completionAddr,
|
|
ce->platform->pciToDma(cr.completionAddr));
|
|
|
|
cePort.dmaAction(MemCmd::WriteReq,
|
|
ce->platform->pciToDma(cr.completionAddr),
|
|
sizeof(completionDataReg), &statusCompleteEvent,
|
|
(uint8_t*)&completionDataReg, latAfterCompletion);
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::writeStatusComplete()
|
|
{
|
|
DPRINTF(DMACopyEngine, "Writing completion status complete\n");
|
|
continueProcessing();
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::fetchNextAddr(Addr address)
|
|
{
|
|
anBegin("FetchNextAddr");
|
|
DPRINTF(DMACopyEngine, "Fetching next address...\n");
|
|
busy = true;
|
|
cePort.dmaAction(MemCmd::ReadReq,
|
|
ce->platform->pciToDma(address + offsetof(DmaDesc, next)),
|
|
sizeof(Addr), &addrCompleteEvent,
|
|
(uint8_t*)curDmaDesc + offsetof(DmaDesc, next), 0);
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::fetchAddrComplete()
|
|
{
|
|
DPRINTF(DMACopyEngine, "Fetching next address complete: %#x\n",
|
|
curDmaDesc->next);
|
|
if (!curDmaDesc->next) {
|
|
DPRINTF(DMACopyEngine, "Got NULL descriptor, nothing more to do\n");
|
|
busy = false;
|
|
nextState = Idle;
|
|
anWait();
|
|
anBegin("Idle");
|
|
inDrain();
|
|
return;
|
|
}
|
|
nextState = DescriptorFetch;
|
|
fetchAddress = curDmaDesc->next;
|
|
if (inDrain()) return;
|
|
fetchDescriptor(curDmaDesc->next);
|
|
}
|
|
|
|
bool
|
|
CopyEngine::CopyEngineChannel::inDrain()
|
|
{
|
|
if (ce->getState() == SimObject::Draining) {
|
|
DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
|
|
assert(drainEvent);
|
|
drainEvent->process();
|
|
drainEvent = NULL;
|
|
}
|
|
|
|
return ce->getState() != SimObject::Running;
|
|
}
|
|
|
|
unsigned int
|
|
CopyEngine::CopyEngineChannel::drain(Event *de)
|
|
{
|
|
if (nextState == Idle || ce->getState() != SimObject::Running)
|
|
return 0;
|
|
unsigned int count = 1;
|
|
count += cePort.drain(de);
|
|
|
|
DPRINTF(Drain, "CopyEngineChannel not drained\n");
|
|
drainEvent = de;
|
|
return count;
|
|
}
|
|
|
|
unsigned int
|
|
CopyEngine::drain(Event *de)
|
|
{
|
|
unsigned int count;
|
|
count = pioPort.drain(de) + dmaPort.drain(de) + configPort.drain(de);
|
|
for (int x = 0;x < chan.size(); x++)
|
|
count += chan[x]->drain(de);
|
|
|
|
if (count)
|
|
changeState(Draining);
|
|
else
|
|
changeState(Drained);
|
|
|
|
DPRINTF(Drain, "CopyEngine not drained\n");
|
|
return count;
|
|
}
|
|
|
|
void
|
|
CopyEngine::serialize(std::ostream &os)
|
|
{
|
|
PciDev::serialize(os);
|
|
regs.serialize(os);
|
|
for (int x =0; x < chan.size(); x++) {
|
|
nameOut(os, csprintf("%s.channel%d", name(), x));
|
|
chan[x]->serialize(os);
|
|
}
|
|
}
|
|
|
|
void
|
|
CopyEngine::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
PciDev::unserialize(cp, section);
|
|
regs.unserialize(cp, section);
|
|
for (int x = 0; x < chan.size(); x++)
|
|
chan[x]->unserialize(cp, csprintf("%s.channel%d", section, x));
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_SCALAR(channelId);
|
|
SERIALIZE_SCALAR(busy);
|
|
SERIALIZE_SCALAR(underReset);
|
|
SERIALIZE_SCALAR(refreshNext);
|
|
SERIALIZE_SCALAR(lastDescriptorAddr);
|
|
SERIALIZE_SCALAR(completionDataReg);
|
|
SERIALIZE_SCALAR(fetchAddress);
|
|
int nextState = this->nextState;
|
|
SERIALIZE_SCALAR(nextState);
|
|
arrayParamOut(os, "curDmaDesc", (uint8_t*)curDmaDesc, sizeof(DmaDesc));
|
|
SERIALIZE_ARRAY(copyBuffer, ce->params()->XferCap);
|
|
cr.serialize(os);
|
|
|
|
}
|
|
void
|
|
CopyEngine::CopyEngineChannel::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_SCALAR(channelId);
|
|
UNSERIALIZE_SCALAR(busy);
|
|
UNSERIALIZE_SCALAR(underReset);
|
|
UNSERIALIZE_SCALAR(refreshNext);
|
|
UNSERIALIZE_SCALAR(lastDescriptorAddr);
|
|
UNSERIALIZE_SCALAR(completionDataReg);
|
|
UNSERIALIZE_SCALAR(fetchAddress);
|
|
int nextState;
|
|
UNSERIALIZE_SCALAR(nextState);
|
|
this->nextState = (ChannelState)nextState;
|
|
arrayParamIn(cp, section, "curDmaDesc", (uint8_t*)curDmaDesc, sizeof(DmaDesc));
|
|
UNSERIALIZE_ARRAY(copyBuffer, ce->params()->XferCap);
|
|
cr.unserialize(cp, section);
|
|
|
|
}
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::restartStateMachine()
|
|
{
|
|
switch(nextState) {
|
|
case AddressFetch:
|
|
fetchNextAddr(lastDescriptorAddr);
|
|
break;
|
|
case DescriptorFetch:
|
|
fetchDescriptor(fetchAddress);
|
|
break;
|
|
case DMARead:
|
|
readCopyBytes();
|
|
break;
|
|
case DMAWrite:
|
|
writeCopyBytes();
|
|
break;
|
|
case CompletionWrite:
|
|
writeCompletionStatus();
|
|
break;
|
|
case Idle:
|
|
break;
|
|
default:
|
|
panic("Unknown state for CopyEngineChannel\n");
|
|
}
|
|
}
|
|
|
|
void
|
|
CopyEngine::resume()
|
|
{
|
|
SimObject::resume();
|
|
for (int x = 0;x < chan.size(); x++)
|
|
chan[x]->resume();
|
|
}
|
|
|
|
|
|
void
|
|
CopyEngine::CopyEngineChannel::resume()
|
|
{
|
|
DPRINTF(DMACopyEngine, "Restarting state machine at state %d\n", nextState);
|
|
restartStateMachine();
|
|
}
|
|
|
|
CopyEngine *
|
|
CopyEngineParams::create()
|
|
{
|
|
return new CopyEngine(this);
|
|
}
|