gem5/cpu/thread_state.hh
Kevin Lim a8b03e4d01 Updates for O3 model.
arch/alpha/isa/decoder.isa:
    Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
    Allow IPR instructions to have flags.
base/traceflags.py:
    Include new trace flags from the two new CPU models.
cpu/SConscript:
    Create the templates for the split mem accessor methods.  Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Update to the BaseDynInst for the new models.

--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-22 18:26:48 -04:00

92 lines
2.2 KiB
C++

#ifndef __CPU_THREAD_STATE_HH__
#define __CPU_THREAD_STATE_HH__
#include "cpu/exec_context.hh"
#if FULL_SYSTEM
class EndQuiesceEvent;
class FunctionProfile;
class ProfileNode;
#else
class Process;
class FunctionalMemory;
#endif
struct ThreadState {
#if FULL_SYSTEM
ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem)
: cpuId(_cpuId), tid(_tid), mem(_mem), lastActivate(0), lastSuspend(0),
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL)
#else
ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem,
Process *_process, short _asid)
: cpuId(_cpuId), tid(_tid), mem(_mem), process(_process), asid(_asid)
#endif
{
funcExeInst = 0;
storeCondFailures = 0;
}
ExecContext::Status status;
int cpuId;
// Index of hardware thread context on the CPU that this represents.
int tid;
Counter numInst;
Stats::Scalar<> numInsts;
Stats::Scalar<> numMemRefs;
// number of simulated loads
Counter numLoad;
Counter startNumLoad;
FunctionalMemory *mem; // functional storage for process address space
#if FULL_SYSTEM
Tick lastActivate;
Tick lastSuspend;
FunctionProfile *profile;
ProfileNode *profileNode;
Addr profilePC;
EndQuiesceEvent *quiesceEvent;
#else
Process *process;
// Address space ID. Note that this is used for TIMING cache
// simulation only; all functional memory accesses should use
// one of the FunctionalMemory pointers above.
short asid;
#endif
/**
* Temporary storage to pass the source address from copy_load to
* copy_store.
* @todo Remove this temporary when we have a better way to do it.
*/
Addr copySrcAddr;
/**
* Temp storage for the physical source address of a copy.
* @todo Remove this temporary when we have a better way to do it.
*/
Addr copySrcPhysAddr;
/*
* number of executed instructions, for matching with syscall trace
* points in EIO files.
*/
Counter funcExeInst;
//
// Count failed store conditionals so we can warn of apparent
// application deadlock situations.
unsigned storeCondFailures;
};
#endif // __CPU_THREAD_STATE_HH__