a8b03e4d01
arch/alpha/isa/decoder.isa: Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model. arch/alpha/isa/pal.isa: Allow IPR instructions to have flags. base/traceflags.py: Include new trace flags from the two new CPU models. cpu/SConscript: Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next). cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Update to the BaseDynInst for the new models. --HG-- extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
227 lines
8 KiB
C++
227 lines
8 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_BPRED_UNIT_HH__
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#define __CPU_O3_BPRED_UNIT_HH__
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// For Addr type.
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#include "arch/isa_traits.hh"
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#include "base/statistics.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/2bit_local_pred.hh"
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#include "cpu/o3/btb.hh"
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#include "cpu/o3/ras.hh"
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#include "cpu/o3/tournament_pred.hh"
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#include <list>
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/**
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* Basically a wrapper class to hold both the branch predictor
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* and the BTB. Right now I'm unsure of the implementation; it would
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* be nicer to have something closer to the CPUPolicy or the Impl where
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* this is just typedefs, but it forces the upper level stages to be
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* aware of the constructors of the BP and the BTB. The nicer thing
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* to do is have this templated on the Impl, accept the usual Params
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* object, and be able to call the constructors on the BP and BTB.
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*/
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template<class Impl>
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class TwobitBPredUnit
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{
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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/**
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* @param params The params object, that has the size of the BP and BTB.
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*/
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TwobitBPredUnit(Params *params);
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/**
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* Registers statistics.
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*/
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void regStats();
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/**
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* Predicts whether or not the instruction is a taken branch, and the
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* target of the branch if it is taken.
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* @param inst The branch instruction.
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* @param PC The predicted PC is passed back through this parameter.
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* @param tid The thread id.
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* @return Returns if the branch is taken or not.
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*/
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bool predict(DynInstPtr &inst, Addr &PC, unsigned tid);
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/**
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* Tells the branch predictor to commit any updates until the given
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* sequence number.
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* @param done_sn The sequence number to commit any older updates up until.
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* @param tid The thread id.
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*/
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void update(const InstSeqNum &done_sn, unsigned tid);
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/**
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* Squashes all outstanding updates until a given sequence number.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, unsigned tid);
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/**
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* Squashes all outstanding updates until a given sequence number, and
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* corrects that sn's update with the proper address and taken/not taken.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param corr_target The correct branch target.
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* @param actually_taken The correct branch direction.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
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bool actually_taken, unsigned tid);
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/**
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* Looks up a given PC in the BP to see if it is taken or not taken.
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* @param inst_PC The PC to look up.
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* @return Whether the branch is taken or not taken.
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*/
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bool BPLookup(Addr &inst_PC)
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{ return BP.lookup(inst_PC); }
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/**
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* Looks up a given PC in the BTB to see if a matching entry exists.
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* @param inst_PC The PC to look up.
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* @return Whether the BTB contains the given PC.
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*/
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bool BTBValid(Addr &inst_PC)
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{ return BTB.valid(inst_PC, 0); }
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/**
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* Looks up a given PC in the BTB to get the predicted target.
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* @param inst_PC The PC to look up.
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* @return The address of the target of the branch.
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*/
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Addr BTBLookup(Addr &inst_PC)
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{ return BTB.lookup(inst_PC, 0); }
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/**
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* Updates the BP with taken/not taken information.
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* @param inst_PC The branch's PC that will be updated.
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* @param taken Whether the branch was taken or not taken.
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* @todo Make this update flexible enough to handle a global predictor.
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*/
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void BPUpdate(Addr &inst_PC, bool taken)
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{ BP.update(inst_PC, taken); }
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/**
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* Updates the BTB with the target of a branch.
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* @param inst_PC The branch's PC that will be updated.
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* @param target_PC The branch's target that will be added to the BTB.
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*/
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void BTBUpdate(Addr &inst_PC, Addr &target_PC)
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{ BTB.update(inst_PC, target_PC,0); }
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private:
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struct PredictorHistory {
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/**
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* Makes a predictor history struct that contains a sequence number,
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* the PC of its instruction, and whether or not it was predicted
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* taken.
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*/
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PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
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const bool pred_taken, const unsigned _tid)
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: seqNum(seq_num), PC(inst_PC), RASTarget(0), globalHistory(0),
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RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
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wasCall(0)
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{ }
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/** The sequence number for the predictor history entry. */
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InstSeqNum seqNum;
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/** The PC associated with the sequence number. */
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Addr PC;
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/** The RAS target (only valid if a return). */
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Addr RASTarget;
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/** The global history at the time this entry was created. */
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unsigned globalHistory;
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/** The RAS index of the instruction (only valid if a call). */
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unsigned RASIndex;
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/** The thread id. */
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unsigned tid;
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/** Whether or not it was predicted taken. */
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bool predTaken;
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/** Whether or not the RAS was used. */
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bool usedRAS;
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/** Whether or not the instruction was a call. */
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bool wasCall;
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};
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typedef std::list<PredictorHistory> History;
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/**
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* The per-thread predictor history. This is used to update the predictor
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* as instructions are committed, or restore it to the proper state after
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* a squash.
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*/
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History predHist[Impl::MaxThreads];
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/** The branch predictor. */
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DefaultBP BP;
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/** The BTB. */
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DefaultBTB BTB;
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/** The per-thread return address stack. */
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ReturnAddrStack RAS[Impl::MaxThreads];
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/** Stat for number of BP lookups. */
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Stats::Scalar<> lookups;
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/** Stat for number of conditional branches predicted. */
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Stats::Scalar<> condPredicted;
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/** Stat for number of conditional branches predicted incorrectly. */
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Stats::Scalar<> condIncorrect;
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/** Stat for number of BTB lookups. */
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Stats::Scalar<> BTBLookups;
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/** Stat for number of BTB hits. */
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Stats::Scalar<> BTBHits;
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/** Stat for number of times the BTB is correct. */
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Stats::Scalar<> BTBCorrect;
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/** Stat for number of times the RAS is used to get a target. */
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Stats::Scalar<> usedRAS;
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/** Stat for number of times the RAS is incorrect. */
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Stats::Scalar<> RASIncorrect;
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};
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#endif // __CPU_O3_BPRED_UNIT_HH__
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