300 lines
32 KiB
Text
300 lines
32 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000003 # Number of seconds simulated
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sim_ticks 2694500 # Number of ticks simulated
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final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 582910 # Simulator instruction rate (inst/s)
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host_op_rate 681582 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 341032781 # Simulator tick rate (ticks/s)
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host_mem_usage 293692 # Number of bytes of host memory used
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host_seconds 0.01 # Real time elapsed on the host
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sim_insts 4591 # Number of instructions simulated
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sim_ops 5377 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
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system.physmem.bytes_read::total 22907 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
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system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s)
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system.membus.trans_dist::ReadReq 5596 # Transaction distribution
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system.membus.trans_dist::ReadResp 5607 # Transaction distribution
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system.membus.trans_dist::WriteReq 913 # Transaction distribution
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system.membus.trans_dist::WriteResp 913 # Transaction distribution
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system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
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system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
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system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
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system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 6531 # Request fanout histogram
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system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram
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system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 4 # Request fanout histogram
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system.membus.snoop_fanout::max_value 5 # Request fanout histogram
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system.membus.snoop_fanout::total 6531 # Request fanout histogram
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
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system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
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system.cpu.checker.dtb.read_hits 0 # DTB read hits
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system.cpu.checker.dtb.read_misses 0 # DTB read misses
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system.cpu.checker.dtb.write_hits 0 # DTB write hits
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system.cpu.checker.dtb.write_misses 0 # DTB write misses
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system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
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system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
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system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.checker.dtb.hits 0 # DTB hits
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system.cpu.checker.dtb.misses 0 # DTB misses
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system.cpu.checker.dtb.accesses 0 # DTB accesses
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system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.checker.itb.inst_hits 0 # ITB inst hits
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system.cpu.checker.itb.inst_misses 0 # ITB inst misses
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system.cpu.checker.itb.read_hits 0 # DTB read hits
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system.cpu.checker.itb.read_misses 0 # DTB read misses
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system.cpu.checker.itb.write_hits 0 # DTB write hits
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system.cpu.checker.itb.write_misses 0 # DTB write misses
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system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.checker.itb.read_accesses 0 # DTB read accesses
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system.cpu.checker.itb.write_accesses 0 # DTB write accesses
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system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.checker.itb.hits 0 # DTB hits
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system.cpu.checker.itb.misses 0 # DTB misses
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system.cpu.checker.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.checker.numCycles 0 # number of cpu cycles simulated
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system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.numCycles 5390 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 4591 # Number of instructions committed
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system.cpu.committedOps 5377 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 203 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4624 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 7607 # number of times the integer registers were read
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system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 1965 # number of memory refs
|
|
system.cpu.num_load_insts 1027 # Number of load instructions
|
|
system.cpu.num_store_insts 938 # Number of store instructions
|
|
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
|
system.cpu.Branches 1007 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 5390 # Class of executed instruction
|
|
|
|
---------- End Simulation Statistics ----------
|