1386 lines
159 KiB
Text
1386 lines
159 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.802895 # Number of seconds simulated
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sim_ticks 2802895103500 # Number of ticks simulated
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final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 967895 # Simulator instruction rate (inst/s)
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host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 18476638236 # Simulator tick rate (ticks/s)
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host_mem_usage 571628 # Number of bytes of host memory used
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host_seconds 151.70 # Real time elapsed on the host
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sim_insts 146829031 # Number of instructions simulated
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sim_ops 178908942 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 631 # Number of DMA write transactions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.dtb.inst_hits 0 # ITB inst hits
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.read_hits 20339962 # DTB read hits
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system.cpu0.dtb.read_misses 6874 # DTB read misses
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system.cpu0.dtb.write_hits 16391171 # DTB write hits
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system.cpu0.dtb.write_misses 1093 # DTB write misses
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system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.read_accesses 20346836 # DTB read accesses
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system.cpu0.dtb.write_accesses 16392264 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dtb.hits 36731133 # DTB hits
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system.cpu0.dtb.misses 7967 # DTB misses
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system.cpu0.dtb.accesses 36739100 # DTB accesses
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system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.itb.inst_hits 97440315 # ITB inst hits
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system.cpu0.itb.inst_misses 3358 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
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system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses
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system.cpu0.itb.hits 97440315 # DTB hits
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system.cpu0.itb.misses 3358 # DTB misses
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system.cpu0.itb.accesses 97443673 # DTB accesses
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system.cpu0.numCycles 5605792176 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.committedInsts 95427853 # Number of instructions committed
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system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed
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system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses
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system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
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system.cpu0.num_func_calls 8000324 # number of times a function call or return occured
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system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls
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system.cpu0.num_int_insts 100763618 # number of integer instructions
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system.cpu0.num_fp_insts 9755 # number of float instructions
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system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read
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system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written
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system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
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system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
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system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read
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system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written
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system.cpu0.num_mem_refs 37874145 # number of memory refs
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system.cpu0.num_load_insts 20597552 # Number of load instructions
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system.cpu0.num_store_insts 17276593 # Number of store instructions
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system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles
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system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles
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|
system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
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|
system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
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|
system.cpu0.Branches 21941792 # Number of branches fetched
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|
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
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|
system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction
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|
system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
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system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
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|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
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system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
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system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction
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system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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|
system.cpu0.op_class::total 116883193 # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed
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system.cpu0.dcache.tags.replacements 693476 # number of replacements
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system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use
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|
system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks.
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system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 769184 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 511648 # number of writebacks
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1109742 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 96332394 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1110263 # number of overall misses
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu0.l2cache.tags.replacements 252403 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits
|
|
system.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits
|
|
system.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 348794 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 192841 # number of writebacks
|
|
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 322042 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 12173884 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2852 # DTB read misses
|
|
system.cpu1.dtb.write_hits 7587193 # DTB write hits
|
|
system.cpu1.dtb.write_misses 506 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 12176736 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 7587699 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 19761077 # DTB hits
|
|
system.cpu1.dtb.misses 3358 # DTB misses
|
|
system.cpu1.dtb.accesses 19764435 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 53671431 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1734 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses
|
|
system.cpu1.itb.hits 53671431 # DTB hits
|
|
system.cpu1.itb.misses 1734 # DTB misses
|
|
system.cpu1.itb.accesses 53673165 # DTB accesses
|
|
system.cpu1.numCycles 5605321082 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 51401178 # Number of instructions committed
|
|
system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 9170823 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 56984089 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1792 # number of float instructions
|
|
system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 20026333 # number of memory refs
|
|
system.cpu1.num_load_insts 12289505 # Number of load instructions
|
|
system.cpu1.num_store_insts 7736828 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
|
|
system.cpu1.Branches 15217445 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 65459288 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
|
|
system.cpu1.dcache.tags.replacements 191938 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 259820 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 120709 # number of writebacks
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 523373 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 53148636 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 523885 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu1.l2cache.tags.replacements 48598 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits
|
|
system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits
|
|
system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 765653 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3489 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 32919 # number of writebacks
|
|
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 499587 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram
|
|
system.iobus.trans_dist::ReadReq 31002 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 31002 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59433 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 23209 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328284 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 107620 # number of replacements
|
|
system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 207975 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.057323 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 45390 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.921509 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 4903951 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 4903951 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 85 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 75 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 28112 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 75977 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 41 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 11436 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 11429 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 127191 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 225760 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 225760 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 516 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 573 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 13918 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 3099 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 17017 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 85 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 28112 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 89895 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 11436 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 14528 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 144208 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 85 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 28112 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 89895 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 11436 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 14528 # number of overall hits
|
|
system.l2c.overall_hits::total 144208 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 16900 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 11311 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 2371 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1120 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 31713 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 9991 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3299 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 13290 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 771 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1177 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1948 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 15826 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 152622 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 16900 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 148107 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16946 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 184335 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 16900 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 148107 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16946 # number of overall misses
|
|
system.l2c.overall_misses::total 184335 # number of overall misses
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 92 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 77 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 45012 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 87288 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 13807 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 12549 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 158904 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 225760 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 225760 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 10507 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 3356 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 823 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2009 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 150714 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 18925 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 169639 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 45012 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 238002 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 94860 # number of writebacks
|
|
system.l2c.writebacks::total 94860 # number of writebacks
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 75978 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 75978 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 30905 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 30905 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 131050 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 196304 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 152218 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 496844 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 496844 # Request fanout histogram
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes)
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system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes)
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system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes)
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system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes)
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|
system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes)
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|
system.toL2Bus.snoops 36713 # Total snoops (count)
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|
system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram
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system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram
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system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram
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system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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|
system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram
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|
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---------- End Simulation Statistics ----------
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