2490 lines
289 KiB
Text
2490 lines
289 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 51.358466 # Number of seconds simulated
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sim_ticks 51358465585500 # Number of ticks simulated
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final_tick 51358465585500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 124397 # Simulator instruction rate (inst/s)
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host_op_rate 146176 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7088870517 # Simulator tick rate (ticks/s)
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host_mem_usage 677952 # Number of bytes of host memory used
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host_seconds 7244.94 # Real time elapsed on the host
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sim_insts 901249371 # Number of instructions simulated
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sim_ops 1059038863 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 144192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 134400 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 3960256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 28248856 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 172736 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 160128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 3375488 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 26920496 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 423040 # Number of bytes read from this memory
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system.physmem.bytes_read::total 63539592 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 3960256 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 3375488 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 7335744 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 82068736 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::total 82089316 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 2253 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2100 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 61879 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 441396 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 2699 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 2502 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 52742 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 420638 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6610 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 992819 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1282324 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1284897 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 2808 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 2617 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 77110 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 550033 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 3363 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 3118 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 65724 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 524169 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 8237 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1237179 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 77110 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 65724 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 142834 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1597959 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1598360 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1597959 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 2808 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 2617 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 77110 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 550434 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 3363 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 3118 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 65724 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 524169 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 8237 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2835539 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 992819 # Number of read requests accepted
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system.physmem.writeReqs 1909642 # Number of write requests accepted
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system.physmem.readBursts 992819 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1909642 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 63506944 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue
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system.physmem.bytesWritten 121761344 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 63539592 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 122072996 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 7111 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 37069 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 60948 # Per bank write bursts
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system.physmem.perBankRdBursts::1 60211 # Per bank write bursts
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system.physmem.perBankRdBursts::2 58469 # Per bank write bursts
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system.physmem.perBankRdBursts::3 57182 # Per bank write bursts
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system.physmem.perBankRdBursts::4 59427 # Per bank write bursts
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system.physmem.perBankRdBursts::5 69894 # Per bank write bursts
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system.physmem.perBankRdBursts::6 60719 # Per bank write bursts
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system.physmem.perBankRdBursts::7 60135 # Per bank write bursts
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system.physmem.perBankRdBursts::8 57063 # Per bank write bursts
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system.physmem.perBankRdBursts::9 84498 # Per bank write bursts
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system.physmem.perBankRdBursts::10 60252 # Per bank write bursts
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system.physmem.perBankRdBursts::11 64911 # Per bank write bursts
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system.physmem.perBankRdBursts::12 58664 # Per bank write bursts
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system.physmem.perBankRdBursts::13 62105 # Per bank write bursts
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system.physmem.perBankRdBursts::14 58293 # Per bank write bursts
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system.physmem.perBankRdBursts::15 59525 # Per bank write bursts
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system.physmem.perBankWrBursts::0 119395 # Per bank write bursts
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system.physmem.perBankWrBursts::1 117730 # Per bank write bursts
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system.physmem.perBankWrBursts::2 117506 # Per bank write bursts
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system.physmem.perBankWrBursts::3 117615 # Per bank write bursts
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system.physmem.perBankWrBursts::4 116969 # Per bank write bursts
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system.physmem.perBankWrBursts::5 124824 # Per bank write bursts
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system.physmem.perBankWrBursts::6 116994 # Per bank write bursts
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system.physmem.perBankWrBursts::7 119672 # Per bank write bursts
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system.physmem.perBankWrBursts::8 117205 # Per bank write bursts
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system.physmem.perBankWrBursts::9 123532 # Per bank write bursts
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system.physmem.perBankWrBursts::10 118074 # Per bank write bursts
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system.physmem.perBankWrBursts::11 121555 # Per bank write bursts
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system.physmem.perBankWrBursts::12 115761 # Per bank write bursts
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system.physmem.perBankWrBursts::13 122535 # Per bank write bursts
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system.physmem.perBankWrBursts::14 116498 # Per bank write bursts
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system.physmem.perBankWrBursts::15 116656 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 94 # Number of times write queue was full causing retry
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system.physmem.totGap 51358464467000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 13 # Read request sizes (log2)
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system.physmem.readPktSize::4 2 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 992804 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 1 # Write request sizes (log2)
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system.physmem.writePktSize::3 2572 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1907069 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 594810 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 261742 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 92458 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 39543 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1048 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 420 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 332 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 232 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 158 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 132 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 123 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 113 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 99 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 824 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 768 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 764 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 757 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 750 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 756 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 760 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 752 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 741 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 741 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 739 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 735 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 737 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 734 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 729 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 38063 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 69896 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 79199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 93003 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 104514 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 119076 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 117779 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 128388 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 124328 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::24 136701 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 126686 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::26 112871 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 105936 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 106364 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 92202 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 90503 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 89684 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 85602 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 5964 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 4975 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 4275 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 4024 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 3728 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 3450 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::39 3239 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 3237 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 3041 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 2905 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 2816 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::44 2728 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 2633 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 2541 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 2466 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 2439 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 2243 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 2077 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 1975 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 1760 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 1504 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 1298 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 1161 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 986 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 827 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 632 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 497 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 378 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 239 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 186 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 225 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 619163 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::mean 299.223151 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::gmean 170.216009 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::stdev 336.259099 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::0-127 254617 41.12% 41.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 146485 23.66% 64.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 55354 8.94% 73.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 28104 4.54% 78.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 20475 3.31% 81.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 12983 2.10% 83.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 10576 1.71% 85.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 9506 1.54% 86.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 81063 13.09% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 619163 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 77925 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 12.733693 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 58.402560 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-511 77917 99.99% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 77925 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 77925 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 24.414771 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 21.404795 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 17.389828 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 83 0.11% 0.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 12 0.02% 0.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 10 0.01% 0.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 84 0.11% 0.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 52239 67.04% 67.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 2830 3.63% 70.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 709 0.91% 71.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 6561 8.42% 80.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 7338 9.42% 89.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 1031 1.32% 90.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 1085 1.39% 92.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 1174 1.51% 93.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 800 1.03% 94.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 285 0.37% 95.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 381 0.49% 95.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 214 0.27% 96.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 366 0.47% 96.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 298 0.38% 96.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 251 0.32% 97.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 217 0.28% 97.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 385 0.49% 97.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 175 0.22% 98.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 111 0.14% 98.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 109 0.14% 98.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 293 0.38% 98.87% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 79 0.10% 98.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::104-107 56 0.07% 99.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 98 0.13% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 168 0.22% 99.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 47 0.06% 99.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 31 0.04% 99.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 43 0.06% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 108 0.14% 99.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 28 0.04% 99.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 23 0.03% 99.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 23 0.03% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 29 0.04% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 14 0.02% 99.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 15 0.02% 99.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 12 0.02% 99.86% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 14 0.02% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 22 0.03% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-171 10 0.01% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 7 0.01% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 16 0.02% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 2 0.00% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 7 0.01% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 2 0.00% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-195 5 0.01% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::196-199 1 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::204-207 1 0.00% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-211 4 0.01% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::212-215 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-219 2 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::220-223 6 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::228-231 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::232-235 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::236-239 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::244-247 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::248-251 2 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 77925 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 27174725250 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 45780275250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 4961480000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 27385.70 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 46135.70 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 2.37 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.24 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 2.38 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 8.84 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 765740 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 1509913 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 77.17 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 79.36 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 17694799.16 # Average gap between requests
|
|
system.physmem.pageHitRate 78.61 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 49399135941008 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 1714971960000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 244357347492 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 2363029200 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 2317843080 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 1289351250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 1264696125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 3798436200 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 3941425800 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 6160568400 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 6167767680 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 3354485153760 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 3354485153760 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 1233743623290 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 1233089726130 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 29732846799750 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 29733420393750 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 34334686961850 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 34334687006325 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 668.530261 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 668.530262 # Core power per rank (mW)
|
|
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
|
system.cpu0.branchPred.lookups 131952150 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 89649773 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 5822015 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 90992883 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 64634149 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 71.032093 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 17244860 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 187476 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 105327476 # DTB read hits
|
|
system.cpu0.dtb.read_misses 614604 # DTB read misses
|
|
system.cpu0.dtb.write_hits 81433492 # DTB write hits
|
|
system.cpu0.dtb.write_misses 261715 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 1084 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 21241 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 54785 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 190 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 8902 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 53829 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 105942080 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 81695207 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 186760968 # DTB hits
|
|
system.cpu0.dtb.misses 876319 # DTB misses
|
|
system.cpu0.dtb.accesses 187637287 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 94794688 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 101824 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 1084 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 21241 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 41122 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 203923 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 94896512 # ITB inst accesses
|
|
system.cpu0.itb.hits 94794688 # DTB hits
|
|
system.cpu0.itb.misses 101824 # DTB misses
|
|
system.cpu0.itb.accesses 94896512 # DTB accesses
|
|
system.cpu0.numCycles 673746678 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 246770894 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 586838334 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 131952150 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 81879009 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 386930341 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 13253583 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 2358226 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 20576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingDrainCycles 5110 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu0.fetch.PendingTrapStallCycles 5338145 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 169787 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 2046 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 94573624 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 3603023 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 38939 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 648221646 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 1.060144 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.307830 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 503028040 77.60% 77.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 18376002 2.83% 80.44% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 18277372 2.82% 83.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 13314289 2.05% 85.31% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 28669690 4.42% 89.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 8974243 1.38% 91.12% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 9730545 1.50% 92.62% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 8410547 1.30% 93.92% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 39440918 6.08% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 648221646 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.195848 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.871007 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 200186064 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 323821330 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 105067312 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 13887509 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 5257280 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 19546951 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 1388336 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 640651678 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 4275147 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 5257280 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 207892852 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 28836524 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 254594010 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 111072647 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 40565977 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 625329125 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 73391 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 2369804 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 1783636 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 20590537 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.FullRegisterEvents 4721 # Number of times there has been no free registers
|
|
system.cpu0.rename.RenamedOperands 598881072 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 965488055 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 739733763 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 970310 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 502829107 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 96051965 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 15333341 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 13384841 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 78497988 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 100792231 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 85691546 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 13482087 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 14436592 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 593155856 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 15408534 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 593869164 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 811141 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 75391106 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 52735595 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 350692 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 648221646 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.916151 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.637744 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 413675393 63.82% 63.82% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 99838135 15.40% 79.22% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 43354420 6.69% 85.91% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 30999055 4.78% 90.69% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 23185151 3.58% 94.27% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 15937923 2.46% 96.72% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 10813303 1.67% 98.39% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 6331141 0.98% 99.37% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 4087125 0.63% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 648221646 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 2980479 25.39% 25.39% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 23946 0.20% 25.60% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 2481 0.02% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.62% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 4885958 41.63% 67.25% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 3844513 32.75% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 402330448 67.75% 67.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 1450246 0.24% 67.99% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 67448 0.01% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 71724 0.01% 68.01% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.01% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.01% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.01% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 107439270 18.09% 86.11% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 82509979 13.89% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 593869164 # Type of FU issued
|
|
system.cpu0.iq.rate 0.881443 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 11737380 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.019764 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 1847356027 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 684092325 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 571253396 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 1152468 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 551459 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 500772 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 604990335 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 616209 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 4719298 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 16584124 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 22051 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 699484 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 8981937 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 3863484 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 8859794 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 5257280 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 15355080 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 11717568 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 608700724 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 1772426 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 100792231 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 85691546 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 13094550 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 251810 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 11354978 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 699484 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 2666409 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 2277536 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 4943945 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 587171511 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 105317678 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 5833659 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 136334 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 186754203 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 108711734 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 81436525 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.871502 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 572939308 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 571754168 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 281506422 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 489082927 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 0.848619 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.575580 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 81075036 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 15057842 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 4452233 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 634439872 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.831521 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.823079 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 439457438 69.27% 69.27% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 96886239 15.27% 84.54% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 33460731 5.27% 89.81% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 15060049 2.37% 92.19% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 10644464 1.68% 93.86% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 6550765 1.03% 94.90% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 5894426 0.93% 95.83% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 4022234 0.63% 96.46% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 22463526 3.54% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 634439872 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 448815056 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 527549931 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 160917716 # Number of memory references committed
|
|
system.cpu0.commit.loads 84208107 # Number of loads committed
|
|
system.cpu0.commit.membars 3677805 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 100249360 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 481111 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 484287281 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 13244362 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 365417797 69.27% 69.27% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 1102287 0.21% 69.48% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 49909 0.01% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 62180 0.01% 69.50% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 84208107 15.96% 85.46% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 76709609 14.54% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 527549931 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 22463526 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 1216684794 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 1231052317 # The number of ROB writes
|
|
system.cpu0.timesIdled 4081993 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 25525032 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 47131326354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 448815056 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 527549931 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 1.501168 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 1.501168 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.666148 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.666148 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 692564361 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 407943900 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 896391 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 528896 # number of floating regfile writes
|
|
system.cpu0.cc_regfile_reads 125905812 # number of cc regfile reads
|
|
system.cpu0.cc_regfile_writes 126977702 # number of cc regfile writes
|
|
system.cpu0.misc_regfile_reads 2322757937 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 15198906 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.replacements 10638925 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.983549 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 304517896 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 10639437 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 28.621617 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 289.769940 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 222.213609 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.565957 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.434011 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 1345465491 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 1345465491 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 79979109 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 80848758 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 160827867 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 67346505 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 67891780 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 135238285 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204132 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 199440 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 403572 # number of SoftPFReq hits
|
|
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171160 # number of WriteInvalidateReq hits
|
|
system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 153591 # number of WriteInvalidateReq hits
|
|
system.cpu0.dcache.WriteInvalidateReq_hits::total 324751 # number of WriteInvalidateReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1784441 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1798021 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 3582462 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2031437 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2062591 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 4094028 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 147325614 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 148740538 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 296066152 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 147529746 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 148939978 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 296469724 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 6500737 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 6533272 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 13034009 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 6519313 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 6481267 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 13000580 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 668156 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 654202 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 1322358 # number of SoftPFReq misses
|
|
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 633593 # number of WriteInvalidateReq misses
|
|
system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607646 # number of WriteInvalidateReq misses
|
|
system.cpu0.dcache.WriteInvalidateReq_misses::total 1241239 # number of WriteInvalidateReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 311874 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 325474 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 637348 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 10 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 13020050 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 13014539 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 26034589 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 13688206 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 13668741 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 27356947 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 111607932917 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111225009746 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 222832942663 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 259750103307 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 246979475075 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 506729578382 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 25310357673 # number of WriteInvalidateReq miss cycles
|
|
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 23982059689 # number of WriteInvalidateReq miss cycles
|
|
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 49292417362 # number of WriteInvalidateReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4526632473 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4625804945 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 9152437418 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 268001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 294001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 371358036224 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 358204484821 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 729562521045 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 371358036224 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 358204484821 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 729562521045 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 86479846 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 87382030 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 173861876 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 73865818 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 74373047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 148238865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 872288 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 853642 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 1725930 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 804753 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 761237 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteInvalidateReq_accesses::total 1565990 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2096315 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2123495 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 4219810 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2031439 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2062601 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 4094040 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 160345664 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 161755077 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 322100741 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 161217952 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 162608719 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 323826671 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075171 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074767 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.074968 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.088259 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087145 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.087700 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765981 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.766366 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766171 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.787314 # miss rate for WriteInvalidateReq accesses
|
|
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.798235 # miss rate for WriteInvalidateReq accesses
|
|
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.792623 # miss rate for WriteInvalidateReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.148772 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153273 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.151037 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000005 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081200 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.080458 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.080827 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084905 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.084059 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.084480 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17168.504574 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17024.396006 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17096.270431 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39843.171099 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.665730 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 38977.459343 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39947.344230 # average WriteInvalidateReq miss latency
|
|
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39467.156353 # average WriteInvalidateReq miss latency
|
|
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39712.269242 # average WriteInvalidateReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14514.298957 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14212.517574 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14360.188497 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26800.100000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24500.083333 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28522.013066 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27523.409382 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 28022.816917 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27129.781377 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26206.106680 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 26668.272635 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 59155859 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 42706 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 3724749 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 967 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.881838 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 44.163392 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 8137324 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 8137324 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3661999 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3663033 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 7325032 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5427863 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5389700 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 10817563 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3334 # number of WriteInvalidateReq MSHR hits
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3491 # number of WriteInvalidateReq MSHR hits
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6825 # number of WriteInvalidateReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 189406 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 198198 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 387604 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 9089862 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 9052733 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 18142595 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 9089862 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 9052733 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 18142595 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2838738 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2870239 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 5708977 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1091450 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1091567 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 2183017 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 661474 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 648177 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1309651 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 630259 # number of WriteInvalidateReq MSHR misses
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 604155 # number of WriteInvalidateReq MSHR misses
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1234414 # number of WriteInvalidateReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122468 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 127276 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 249744 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 10 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3930188 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3961806 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 7891994 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4591662 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4609983 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 9201645 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43024166867 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43656462738 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86680629605 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40600883832 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 38849310828 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79450194660 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13171462044 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12577725489 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25749187533 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 23923452719 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 22638090123 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 46561542842 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1614671914 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1630090692 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3244762606 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 247999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 269999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83625050699 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 82505773566 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 166130824265 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 96796512743 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 95083499055 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 191880011798 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2877179750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2839380752 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716560502 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2798393044 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2781680461 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5580073505 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675572794 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5621061213 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296634007 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032825 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032847 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032836 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014776 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014677 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014726 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758321 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759308 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758809 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.783171 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793649 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.788264 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058421 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059937 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059184 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000005 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024511 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024493 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.024502 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028481 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15156.089384 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15210.044438 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15183.215768 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37199.032326 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35590.404279 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36394.675195 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19912.289892 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19404.769822 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19661.106305 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37958.129466 # average WriteInvalidateReq mshr miss latency
|
|
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37470.665844 # average WriteInvalidateReq mshr miss latency
|
|
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37719.551821 # average WriteInvalidateReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13184.439315 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12807.526101 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12992.354595 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24799.900000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22499.916667 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21277.620994 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20825.293708 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21050.551263 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21080.931642 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20625.563924 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20852.794451 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 16118591 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.955303 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 173100510 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 16119103 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 10.738843 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 13625340000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.422577 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.532726 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535982 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.463931 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 206488523 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 206488523 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 85967347 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 87133163 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 173100510 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 85967347 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 87133163 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 173100510 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 85967347 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 87133163 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 173100510 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 8593751 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 8674986 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 17268737 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 8593751 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 8674986 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 17268737 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 8593751 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 8674986 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 17268737 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 114914016470 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 115519885429 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 230433901899 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 114914016470 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 115519885429 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 230433901899 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 114914016470 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 115519885429 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 230433901899 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 94561098 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 95808149 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 190369247 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 94561098 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 95808149 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 190369247 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 94561098 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 95808149 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 190369247 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090880 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090545 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.090712 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090880 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090545 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.090712 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090880 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090545 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.090712 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13371.811270 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13316.434796 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13343.992783 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13371.811270 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13316.434796 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13343.992783 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13371.811270 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13316.434796 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13343.992783 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 69035 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 6155 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.216084 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 567050 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 582411 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 1149461 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 567050 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu1.inst 582411 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 1149461 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 567050 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu1.inst 582411 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 1149461 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8026701 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8092575 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 16119276 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8026701 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 8092575 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 16119276 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8026701 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8092575 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 16119276 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93925882851 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 94357511095 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 188283393946 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93925882851 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 94357511095 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 188283393946 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93925882851 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 94357511095 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 188283393946 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 916338250 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 595537750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1511876000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 916338250 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 595537750 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1511876000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084884 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084466 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084674 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084884 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084466 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.084674 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084884 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084466 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.084674 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11701.679538 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11659.763560 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11680.635901 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11701.679538 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11659.763560 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11680.635901 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11701.679538 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11659.763560 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11680.635901 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 133577738 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 90779695 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 5949901 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 90899106 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 65330171 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 71.871082 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 17378415 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 188946 # Number of incorrect RAS predictions.
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 106064392 # DTB read hits
|
|
system.cpu1.dtb.read_misses 610373 # DTB read misses
|
|
system.cpu1.dtb.write_hits 82025488 # DTB write hits
|
|
system.cpu1.dtb.write_misses 271302 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 1088 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 22250 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 55877 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 8683 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 56886 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 106674765 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 82296790 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 188089880 # DTB hits
|
|
system.cpu1.dtb.misses 881675 # DTB misses
|
|
system.cpu1.dtb.accesses 188971555 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 96043604 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 103294 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 1088 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 22250 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 41299 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 205516 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 96146898 # ITB inst accesses
|
|
system.cpu1.itb.hits 96043604 # DTB hits
|
|
system.cpu1.itb.misses 103294 # DTB misses
|
|
system.cpu1.itb.accesses 96146898 # DTB accesses
|
|
system.cpu1.numCycles 675301208 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 248765293 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 593949498 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 133577738 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 82708586 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 386843919 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 13545666 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.TlbCycles 2415137 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu1.fetch.MiscStallCycles 21504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingDrainCycles 4007 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu1.fetch.PendingTrapStallCycles 5459319 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 169387 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 1822 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 95816300 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 3685759 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.ItlbSquashes 39432 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 650452950 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.068285 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.315163 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 503682671 77.44% 77.44% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 18498717 2.84% 80.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 18563467 2.85% 83.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 13597541 2.09% 85.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 28733288 4.42% 89.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 9099977 1.40% 91.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 9814186 1.51% 92.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 8571904 1.32% 93.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 39891199 6.13% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 650452950 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.197805 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 0.879533 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 201647992 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 323236826 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 106239229 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 13947017 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 5379639 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 19860273 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 1413177 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 647237018 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 4350385 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 5379639 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 209424655 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 28067269 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 255930457 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 112228565 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 39419858 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 631550288 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 96632 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 2287540 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 1813390 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 19429955 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.FullRegisterEvents 4996 # Number of times there has been no free registers
|
|
system.cpu1.rename.RenamedOperands 604714007 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 972949887 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 746652224 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 816553 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 506435319 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 98278683 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 15335388 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 13342018 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 78452935 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 101901110 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 86377507 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 13921613 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 14837029 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 598946566 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 15418828 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 598874973 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 821829 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 77129289 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 53862821 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 352968 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 650452950 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.920705 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.641335 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 414330356 63.70% 63.70% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 100076970 15.39% 79.08% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 43847279 6.74% 85.83% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 31289942 4.81% 90.64% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 23378361 3.59% 94.23% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 16103120 2.48% 96.71% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 10912961 1.68% 98.38% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 6384879 0.98% 99.37% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 4129082 0.63% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 650452950 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 3013028 25.67% 25.67% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 23161 0.20% 25.86% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 2816 0.02% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 2 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.89% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 4848351 41.30% 67.19% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 3852019 32.81% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 405949153 67.79% 67.79% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 1474390 0.25% 68.03% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 66030 0.01% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 142 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 56962 0.01% 68.05% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 108207982 18.07% 86.12% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 83120313 13.88% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 598874973 # Type of FU issued
|
|
system.cpu1.iq.rate 0.886826 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 11739377 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.019602 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 1859775645 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 691731884 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 576296193 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 988457 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 469794 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 425393 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 610086136 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 528213 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 4764786 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 16932520 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 21750 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 718636 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 9175857 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 3929336 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 8527630 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 5379639 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 15396107 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 10835641 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 614503705 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 1815595 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 101901110 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 86377507 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 13042378 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 259470 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 10465486 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 718636 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 2720399 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 2342418 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 5062817 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 592014750 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 106053814 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 5994040 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 138311 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 188080635 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 109728675 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 82026821 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.876668 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 577948748 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 576721586 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 284303568 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 493660086 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 0.854021 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.575910 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 82926260 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 15065860 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 4556436 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 636355753 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.835207 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.827690 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 440359254 69.20% 69.20% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 97084176 15.26% 84.46% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 33726039 5.30% 89.76% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 15156809 2.38% 92.14% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 10762314 1.69% 93.83% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 6601636 1.04% 94.87% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 5939289 0.93% 95.80% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 4020807 0.63% 96.43% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 22705429 3.57% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 636355753 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 452434315 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 531488932 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 162170239 # Number of memory references committed
|
|
system.cpu1.commit.loads 84968589 # Number of loads committed
|
|
system.cpu1.commit.membars 3740598 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 101032588 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 407528 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 487762142 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 13294479 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 368091914 69.26% 69.26% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 1129647 0.21% 69.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 49240 0.01% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 47892 0.01% 69.49% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 84968589 15.99% 85.47% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 77201650 14.53% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 531488932 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 22705429 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 1224024924 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 1242947045 # The number of ROB writes
|
|
system.cpu1.timesIdled 4091922 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 24848258 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 54236174505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 452434315 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 531488932 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 1.492595 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 1.492595 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.669974 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.669974 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 697864723 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 411651158 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 767907 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 473740 # number of floating regfile writes
|
|
system.cpu1.cc_regfile_reads 126991866 # number of cc regfile reads
|
|
system.cpu1.cc_regfile_writes 128085324 # number of cc regfile writes
|
|
system.cpu1.misc_regfile_reads 2338745159 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 15183498 # number of misc regfile writes
|
|
system.iobus.trans_dist::ReadReq 40379 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40379 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136733 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 30069 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 354224 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7492654 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 1042420321 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 178996533 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115458 # number of replacements
|
|
system.iocache.tags.tagsinuse 10.429567 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 13090570223000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.541524 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 6.888043 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.221345 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.430503 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.651848 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1039650 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
|
|
system.iocache.overall_misses::total 8853 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1921756799 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1927241799 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28951102989 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 28951102989 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1921756799 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1927580799 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1921756799 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1927580799 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 218059.321343 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 217767.434915 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271423.376106 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 271423.376106 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 218059.321343 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 217731.932565 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 218059.321343 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 217731.932565 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 227766 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 27719 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 8.216963 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106630 # number of writebacks
|
|
system.iocache.writebacks::total 106630 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8813 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8853 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1463357813 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1466918813 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23404023041 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23404023041 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1463357813 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1467101813 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1463357813 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1467101813 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166045.366277 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 165753.538192 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219418.201464 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219418.201464 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 166045.366277 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 165718.040551 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 166045.366277 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 165718.040551 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 1389484 # number of replacements
|
|
system.l2c.tags.tagsinuse 65352.106394 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 31455593 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 1452181 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 21.660931 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 2484843000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 35806.671040 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 143.176301 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 245.153324 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 3359.514416 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 11467.907347 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 184.237244 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 273.594467 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 3844.520884 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 10027.331371 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.546366 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002185 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003741 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.051262 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.174986 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002811 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.004175 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.058663 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.153005 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.997194 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 343 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 62354 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 341 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 538 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2779 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 53889 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.005234 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 295633480 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 295633480 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 538849 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 186240 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 7977279 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 3458474 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 540473 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 189439 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 8047769 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 3485516 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 24424039 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 8137324 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 8137324 # number of Writeback hits
|
|
system.l2c.WriteInvalidateReq_hits::cpu0.data 356242 # number of WriteInvalidateReq hits
|
|
system.l2c.WriteInvalidateReq_hits::cpu1.data 359953 # number of WriteInvalidateReq hits
|
|
system.l2c.WriteInvalidateReq_hits::total 716195 # number of WriteInvalidateReq hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 4893 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 5150 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 10043 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 790931 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 806807 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 1597738 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 538849 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 186240 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 7977279 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 4249405 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 540473 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 189439 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 8047769 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 4292323 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 26021777 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 538849 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 186240 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 7977279 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 4249405 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 540473 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 189439 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 8047769 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 4292323 # number of overall hits
|
|
system.l2c.overall_hits::total 26021777 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 2272 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2136 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 49402 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 157936 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 2713 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 2545 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 44633 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 153451 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 415088 # number of ReadReq misses
|
|
system.l2c.WriteInvalidateReq_misses::cpu0.data 274017 # number of WriteInvalidateReq misses
|
|
system.l2c.WriteInvalidateReq_misses::cpu1.data 244202 # number of WriteInvalidateReq misses
|
|
system.l2c.WriteInvalidateReq_misses::total 518219 # number of WriteInvalidateReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 17737 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 18576 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 36313 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 3 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 284159 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 267759 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 551918 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 2272 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2136 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 49402 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 442095 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 2713 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 2545 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 44633 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 421210 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 967006 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 2272 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2136 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 49402 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 442095 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 2713 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 2545 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 44633 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 421210 # number of overall misses
|
|
system.l2c.overall_misses::total 967006 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 184273245 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 176430743 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 3875377998 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 13368382174 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 220451240 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 205887741 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 3497850741 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 13033563402 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 34562217284 # number of ReadReq miss cycles
|
|
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 1654929 # number of WriteInvalidateReq miss cycles
|
|
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 1558933 # number of WriteInvalidateReq miss cycles
|
|
system.l2c.WriteInvalidateReq_miss_latency::total 3213862 # number of WriteInvalidateReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 209908987 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 215407746 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 425316733 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 146000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 146000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 27816673691 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 25868839673 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 53685513364 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 184273245 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 176430743 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 3875377998 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 41185055865 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 220451240 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 205887741 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 3497850741 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 38902403075 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 88247730648 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 184273245 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 176430743 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 3875377998 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 41185055865 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 220451240 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 205887741 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 3497850741 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 38902403075 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 88247730648 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 541121 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 188376 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 8026681 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 3616410 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 543186 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 191984 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 8092402 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 3638967 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 24839127 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 8137324 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 8137324 # number of Writeback accesses(hits+misses)
|
|
system.l2c.WriteInvalidateReq_accesses::cpu0.data 630259 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.l2c.WriteInvalidateReq_accesses::cpu1.data 604155 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.l2c.WriteInvalidateReq_accesses::total 1234414 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 22630 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 23726 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 46356 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 10 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 1075090 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 1074566 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 2149656 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 541121 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 188376 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 8026681 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 4691500 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 543186 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 191984 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 8092402 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 4713533 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 26988783 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 541121 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 188376 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 8026681 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 4691500 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 543186 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 191984 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 8092402 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 4713533 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 26988783 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004199 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011339 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.006155 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.043672 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004995 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.013256 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.005515 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.042169 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.016711 # miss rate for ReadReq accesses
|
|
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.434769 # miss rate for WriteInvalidateReq accesses
|
|
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.404204 # miss rate for WriteInvalidateReq accesses
|
|
system.l2c.WriteInvalidateReq_miss_rate::total 0.419810 # miss rate for WriteInvalidateReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.783783 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782939 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.783351 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.300000 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.264312 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.249179 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.256747 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004199 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.011339 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.006155 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.094233 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004995 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.013256 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.005515 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.089362 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.035830 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004199 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.011339 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.006155 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.094233 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004995 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.013256 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.005515 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.089362 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.035830 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81106.181778 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82598.662453 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 78445.771386 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 84644.300058 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81257.368227 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80898.915914 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78369.160509 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 84936.321054 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 83264.795137 # average ReadReq miss latency
|
|
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 6.039512 # average WriteInvalidateReq miss latency
|
|
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 6.383785 # average WriteInvalidateReq miss latency
|
|
system.l2c.WriteInvalidateReq_avg_miss_latency::total 6.201745 # average WriteInvalidateReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11834.525963 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11596.024225 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 11712.519841 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 48666.666667 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 48666.666667 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 97891.228823 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96612.400229 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 97270.814440 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81106.181778 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82598.662453 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 78445.771386 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 93158.836596 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81257.368227 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80898.915914 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 78369.160509 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 92358.688243 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 91258.720885 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81106.181778 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82598.662453 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 78445.771386 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 93158.836596 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81257.368227 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80898.915914 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 78369.160509 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 92358.688243 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 91258.720885 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 1175694 # number of writebacks
|
|
system.l2c.writebacks::total 1175694 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 19 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 36 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu0.data 13 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 14 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 43 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.data 8 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.dtb.walker 19 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.itb.walker 36 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.data 13 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.dtb.walker 14 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.itb.walker 43 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.data 8 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.dtb.walker 19 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.itb.walker 36 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.data 13 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.dtb.walker 14 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.itb.walker 43 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.data 8 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 137 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2253 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2100 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 49400 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 157923 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2699 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2502 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 44631 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 153443 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 414951 # number of ReadReq MSHR misses
|
|
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 274017 # number of WriteInvalidateReq MSHR misses
|
|
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 244202 # number of WriteInvalidateReq MSHR misses
|
|
system.l2c.WriteInvalidateReq_mshr_misses::total 518219 # number of WriteInvalidateReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 17737 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18576 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 36313 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 284159 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 267759 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 551918 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2253 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 2100 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 49400 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 442082 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2699 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.itb.walker 2502 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 44631 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 421202 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 966869 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2253 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 2100 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 49400 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 442082 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2699 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.itb.walker 2502 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 44631 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 421202 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 966869 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 154831495 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 147977993 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3255321002 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11404425184 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 185796240 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 171797741 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2937376759 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11125453714 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 29382980128 # number of ReadReq MSHR miss cycles
|
|
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10490770082 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9554022676 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.l2c.WriteInvalidateReq_mshr_miss_latency::total 20044792758 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 177667232 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 186014070 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 363681302 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 132001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 132001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 24275927309 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 22531972819 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 46807900128 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 154831495 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 147977993 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 3255321002 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 35680352493 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 185796240 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 171797741 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 2937376759 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 33657426533 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 76190880256 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 154831495 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 147977993 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 3255321002 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 35680352493 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 185796240 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 171797741 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 2937376759 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 33657426533 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 76190880256 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 654614249 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2657099750 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 425309250 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2619741250 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 6356764499 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2581434500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2590216000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 5171650500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 654614249 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5238534250 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 425309250 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5209957250 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 11528414999 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004164 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011148 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.006154 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.043668 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004969 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013032 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005515 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042167 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.016706 # mshr miss rate for ReadReq accesses
|
|
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.434769 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.404204 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.419810 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.783783 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.782939 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.783351 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.300000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.264312 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249179 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.256747 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004164 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011148 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006154 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.094230 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004969 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.013032 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005515 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.089360 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.035825 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004164 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011148 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006154 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.094230 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004969 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013032 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005515 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.089360 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.035825 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65897.186275 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72215.099662 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65814.719791 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72505.449672 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 70810.722538 # average ReadReq mshr miss latency
|
|
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38285.106698 # average WriteInvalidateReq mshr miss latency
|
|
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39123.441561 # average WriteInvalidateReq mshr miss latency
|
|
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38680.157922 # average WriteInvalidateReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.757738 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10013.677326 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10015.181946 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 44000.333333 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44000.333333 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85430.788076 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84150.197823 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 84809.519037 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65897.186275 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80709.806083 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65814.719791 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79908.040638 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 78801.657987 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68722.367954 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70465.710952 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65897.186275 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80709.806083 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68838.918118 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68664.165068 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65814.719791 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79908.040638 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 78801.657987 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 478201 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 478201 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 33860 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 33860 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1282324 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 624745 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 624745 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 37074 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 37077 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 551298 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 551298 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6868 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4264222 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 4394358 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335421 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 335421 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 4729779 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13736 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 171538732 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 171711000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14073856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 14073856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 185784856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 2907 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2919339 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 2919339 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2919339 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 99723000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 5540499 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 18597273982 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 9904783124 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 186654467 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.toL2Bus.trans_dist::ReadReq 25451799 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 25443711 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 33860 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 33860 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 8137324 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 1341081 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateResp 1234414 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 46359 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 46371 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 2149656 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 2149656 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32279635 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29644963 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 905204 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2573359 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 65403161 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032942144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1201952920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3042880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8674456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 2246612400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 665707 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 37265900 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 5.003100 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.055590 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 37150380 99.69% 99.69% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 115520 0.31% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 37265900 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 56232033216 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 3430500 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 72693447528 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 43148678653 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 527770675 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 1503131700 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 16411 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|