528 lines
59 KiB
Text
528 lines
59 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 79580 # Simulator instruction rate (inst/s)
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host_mem_usage 255900 # Number of bytes of host memory used
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host_seconds 7569.27 # Real time elapsed on the host
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host_tick_rate 25961971 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 602359865 # Number of instructions simulated
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sim_seconds 0.196513 # Number of seconds simulated
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sim_ticks 196513140500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 75744427 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 81879675 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 1640 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 3832102 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 81880205 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 88398894 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1393010 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 70828614 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 7897771 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 379244728 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.588315 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.904338 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56% 32.56% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44% 65.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60% 80.60% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87% 85.47% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54% 90.01% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79% 93.80% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00% 95.81% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11% 97.92% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 379244728 # Number of insts commited each cycle
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system.cpu.commit.COM:count 602359916 # Number of instructions committed
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system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
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system.cpu.commit.COM:function_calls 997573 # Number of function calls committed.
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system.cpu.commit.COM:int_insts 533522691 # Number of committed integer instructions.
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system.cpu.commit.COM:loads 148952607 # Number of loads committed
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system.cpu.commit.COM:membars 1328 # Number of memory barriers committed
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system.cpu.commit.COM:refs 219173633 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 3891220 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 602359916 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 6310 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 86859726 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 602359865 # Number of Instructions Simulated
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system.cpu.committedInsts_total 602359865 # Number of Instructions Simulated
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system.cpu.cpi 0.652478 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.652478 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 1356 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 10607.142857 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_hits 1342 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 148500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.010324 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 14 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 14 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.ReadReq_accesses 139395234 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 13041.881358 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7904.223289 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 139153026 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3158848000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.001738 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 242208 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 46247 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1548919500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 195961 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 1340 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 1340 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 17910.212192 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10351.034278 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 67926304 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 26708191996 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.021482 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1491227 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1243368 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2565597005 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 247859 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 4376.771337 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 466.592209 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 2191 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 9589506 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 208812765 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 17229.974009 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 207079330 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 29867039996 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.008301 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1733435 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1289615 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4114516505 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.002125 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 443820 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999719 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4094.849519 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 208812765 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 17229.974009 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 207079330 # number of overall hits
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system.cpu.dcache.overall_miss_latency 29867039996 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.008301 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1733435 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1289615 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4114516505 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.002125 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 443820 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 439722 # number of replacements
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system.cpu.dcache.sampled_refs 443818 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.849519 # Cycle average of tags in use
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system.cpu.dcache.total_refs 207082021 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 89315000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 394264 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 64227537 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 1274 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 5983982 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 722350979 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 163737957 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 138388023 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 12871984 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 4747 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 12891210 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 88398894 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 71395519 # Number of cache lines fetched
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system.cpu.fetch.Cycles 153789076 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 942755 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 689805737 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 4451587 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.224919 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 71395519 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 77137437 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.755114 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 392116711 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.872365 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.899483 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 238327790 60.78% 60.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 25111973 6.40% 67.18% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 18227974 4.65% 71.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 22524916 5.74% 77.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 11352449 2.90% 80.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 12221762 3.12% 83.59% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 4491606 1.15% 84.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 7291145 1.86% 86.59% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 52567096 13.41% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 392116711 # Number of instructions fetched each cycle (Total)
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system.cpu.fp_regfile_reads 16 # number of floating regfile reads
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system.cpu.icache.ReadReq_accesses 71395519 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 35429.359823 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34341.412742 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 71394613 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 32099000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 906 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 184 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 24794500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 99159.184722 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 71395519 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 35429.359823 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency
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system.cpu.icache.demand_hits 71394613 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 32099000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
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system.cpu.icache.demand_misses 906 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 184 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 24794500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.307172 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 629.087764 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 71395519 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 35429.359823 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 34341.412742 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 71394613 # number of overall hits
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system.cpu.icache.overall_miss_latency 32099000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
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system.cpu.icache.overall_misses 906 # number of overall misses
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system.cpu.icache.overall_mshr_hits 184 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 24794500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 31 # number of replacements
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system.cpu.icache.sampled_refs 720 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 629.087764 # Cycle average of tags in use
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system.cpu.icache.total_refs 71394613 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 909571 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 73704412 # Number of branches executed
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system.cpu.iew.EXEC:nop 61098 # number of nop insts executed
|
|
system.cpu.iew.EXEC:rate 1.622472 # Inst execution rate
|
|
system.cpu.iew.EXEC:refs 239165331 # number of memory reference insts executed
|
|
system.cpu.iew.EXEC:stores 73423365 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 736448308 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 631945179 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.594878 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 438096934 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 1.607895 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 632881856 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 4305441 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 811047 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 176106355 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 5819 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 2956217 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 82187861 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 689217371 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 165741966 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 6134058 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 637674087 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 25252 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 3721 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 12871984 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 65726 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 8982 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 25082678 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 87734 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 611520 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 15892 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 27153747 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 11966835 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 611520 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 628522 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 3676919 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.int_regfile_reads 1724767298 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 495432855 # number of integer regfile writes
|
|
system.cpu.ipc 1.532620 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.532620 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 400863775 62.26% 62.26% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 6585 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 168265891 26.14% 88.40% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 74671891 11.60% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0::total 643808145 # Type of FU issued
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 3945011 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.006128 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 107679 2.73% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.73% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 3407280 86.37% 89.10% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 430052 10.90% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 392116711 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.641879 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.551770 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 108904518 27.77% 27.77% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 107421508 27.40% 55.17% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 76290088 19.46% 74.62% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 48454562 12.36% 86.98% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 26882762 6.86% 93.84% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 16851716 4.30% 98.14% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 5414053 1.38% 99.52% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 1011203 0.26% 99.77% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 886301 0.23% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 392116711 # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:rate 1.638079 # Inst issue rate
|
|
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
|
|
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
|
system.cpu.iq.int_alu_accesses 647753136 # Number of integer alu accesses
|
|
system.cpu.iq.int_inst_queue_reads 1684034505 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 631945163 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.int_inst_queue_writes 776263645 # Number of integer instruction queue writes
|
|
system.cpu.iq.iqInstsAdded 689149113 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 643808145 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 7160 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 86496318 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 356529 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 850 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 162226931 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 247858 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.577877 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.064273 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_hits 189420 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2006502500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.235772 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 58438 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825490000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235772 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 58438 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 196680 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34348.019439 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.694669 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 163962 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 1123798500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.166351 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 32718 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1017300500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166321 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 32712 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 394264 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 394264 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6213.636364 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 4.739861 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 330 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 2050500 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 444538 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34340.043442 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 353382 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 3130301000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.205058 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 91156 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 2842790500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.205044 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 91150 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_%::0 0.057260 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_%::1 0.487109 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_blocks::0 1876.282231 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 15961.603623 # Average occupied blocks per context
|
|
system.cpu.l2cache.overall_accesses 444538 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34340.043442 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.047175 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 353382 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 3130301000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.205058 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 91156 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 2842790500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.205044 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 91150 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 72953 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 88472 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 17837.885854 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 419345 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 58134 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 25914382 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 23086559 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 176106355 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 82187861 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.misc_regfile_reads 922126404 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2684 # number of misc regfile writes
|
|
system.cpu.numCycles 393026282 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.rename.RENAME:BlockCycles 9628088 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 471021820 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 50048668 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 176696020 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1915065 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 2034394520 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 711291370 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 553214444 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 138291459 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 12871984 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 54521168 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 82192621 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
|
|
system.cpu.rename.RENAME:int_rename_lookups 2034394424 # Number of integer rename lookups
|
|
system.cpu.rename.RENAME:serializeStallCycles 107992 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 6480 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 91409775 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 6477 # count of temporary serializing insts renamed
|
|
system.cpu.rob.rob_reads 1060565987 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1391311417 # The number of ROB writes
|
|
system.cpu.timesIdled 36947 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|