9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
28 lines
1,006 B
Text
Executable file
28 lines
1,006 B
Text
Executable file
Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout
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Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr
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M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Aug 26 2010 13:03:41
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M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
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M5 started Aug 26 2010 13:03:44
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M5 executing on zizzer
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command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Begining test of difficult SPARC instructions...
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LDSTUB: Passed
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SWAP: Passed
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CAS FAIL: Passed
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CAS WORK: Passed
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CASX FAIL: Passed
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CASX WORK: Passed
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LDTX: Passed
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LDTW: Passed
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STTW: Passed
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Done
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Exiting @ tick 41800000 because target called exit()
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