9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
190 lines
3.3 KiB
INI
190 lines
3.3 KiB
INI
[root]
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type=Root
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children=system
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dummy=0
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache dtb icache itb l2cache toL2Bus tracer workload
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checker=Null
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clock=500
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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progress_interval=0
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=2
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block_size=64
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forward_snoops=true
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hash_delay=1
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latency=1000
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max_miss_count=0
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mshrs=10
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=262144
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.port[1]
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[system.cpu.dtb]
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type=SparcTLB
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size=64
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[system.cpu.icache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=2
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block_size=64
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forward_snoops=true
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hash_delay=1
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latency=1000
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max_miss_count=0
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mshrs=10
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=131072
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.port[0]
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[system.cpu.itb]
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type=SparcTLB
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size=64
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[system.cpu.l2cache]
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type=BaseCache
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addr_range=0:18446744073709551615
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assoc=2
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block_size=64
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forward_snoops=true
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hash_delay=1
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latency=10000
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max_miss_count=0
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mshrs=10
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num_cpus=1
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=100000
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prefetch_on_access=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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repl=Null
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size=2097152
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.port[2]
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mem_side=system.membus.port[1]
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[system.cpu.toL2Bus]
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type=Bus
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block_size=64
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bus_id=0
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clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
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[system.cpu.tracer]
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type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=insttest
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cwd=
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
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gid=100
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input=cin
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
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[system.membus]
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type=Bus
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block_size=64
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bus_id=0
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clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.physmem.port[0] system.cpu.l2cache.mem_side
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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