6b4396111b
cpu/static_inst.hh: Updates for new CPU, also include a classification of quiesce instructions. --HG-- extra : convert_revision : a34cd56da88fe57d7de24674fbb375bbf13f887f
766 lines
21 KiB
C++
766 lines
21 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/isa_traits.hh"
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#include "base/str.hh"
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#include "cpu/ozone/lw_lsq.hh"
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template <class Impl>
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OzoneLWLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(DynInstPtr &_inst,
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BackEnd *_be,
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Event *wb_event,
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OzoneLWLSQ<Impl> *lsq_ptr)
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: Event(&mainEventQueue),
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inst(_inst),
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be(_be),
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wbEvent(wb_event),
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lsqPtr(lsq_ptr)
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{
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this->setFlags(Event::AutoDelete);
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
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{
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DPRINTF(OzoneLSQ, "Cache miss complete for store [sn:%lli]\n",
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inst->seqNum);
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//lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
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// lsqPtr->cpu->wakeCPU();
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if (wbEvent) {
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wbEvent->process();
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delete wbEvent;
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}
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lsqPtr->completeStore(inst->sqIdx);
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be->removeDcacheMiss(inst);
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}
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template <class Impl>
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const char *
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OzoneLWLSQ<Impl>::StoreCompletionEvent::description()
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{
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return "LSQ store completion event";
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}
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template <class Impl>
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OzoneLWLSQ<Impl>::OzoneLWLSQ()
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: loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
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loadBlockedHandled(false)
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{
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}
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template<class Impl>
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void
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OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
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unsigned maxSQEntries, unsigned id)
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{
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DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
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lsqID = id;
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LQEntries = maxLQEntries;
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SQEntries = maxSQEntries;
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for (int i = 0; i < LQEntries * 10; i++) {
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LQIndices.push(i);
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SQIndices.push(i);
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}
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// May want to initialize these entries to NULL
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// loadHead = loadTail = 0;
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// storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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cachePorts = params->cachePorts;
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dcacheInterface = params->dcacheInterface;
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loadFaultInst = storeFaultInst = memDepViolator = NULL;
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blockedLoadSeqNum = 0;
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}
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template<class Impl>
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std::string
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OzoneLWLSQ<Impl>::name() const
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{
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return "lsqunit";
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}
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template<class Impl>
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void
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OzoneLWLSQ<Impl>::clearLQ()
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{
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loadQueue.clear();
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}
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template<class Impl>
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void
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OzoneLWLSQ<Impl>::clearSQ()
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{
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storeQueue.clear();
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}
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template<class Impl>
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void
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OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
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{
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DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
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pTable = pt_ptr;
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}
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template<class Impl>
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void
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OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
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{
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assert( size >= LQEntries);
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if (size > LQEntries) {
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while (size > loadQueue.size()) {
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DynInstPtr dummy;
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loadQueue.push_back(dummy);
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LQEntries++;
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}
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} else {
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LQEntries = size;
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}
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}
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template<class Impl>
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void
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OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
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{
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if (size > SQEntries) {
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while (size > storeQueue.size()) {
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SQEntry dummy;
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storeQueue.push_back(dummy);
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SQEntries++;
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}
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} else {
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SQEntries = size;
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}
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
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{
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// Make sure we really have a memory reference.
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assert(inst->isMemRef());
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// Make sure it's one of the two classes of memory references.
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assert(inst->isLoad() || inst->isStore());
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if (inst->isLoad()) {
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insertLoad(inst);
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} else {
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insertStore(inst);
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}
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// inst->setInLSQ();
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
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{
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assert(!LQIndices.empty());
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int load_index = LQIndices.front();
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LQIndices.pop();
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DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
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load_inst->readPC(), load_index, load_inst->seqNum);
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load_inst->lqIdx = load_index;
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loadQueue.push_front(load_inst);
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LQItHash[load_index] = loadQueue.begin();
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++loads;
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
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{
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// Make sure it is not full before inserting an instruction.
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assert(stores - storesToWB < SQEntries);
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assert(!SQIndices.empty());
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int store_index = SQIndices.front();
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SQIndices.pop();
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DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
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store_inst->readPC(), store_index, store_inst->seqNum);
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store_inst->sqIdx = store_index;
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SQEntry entry(store_inst);
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if (loadQueue.empty()) {
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entry.lqIt = loadQueue.end();
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} else {
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entry.lqIt = loadQueue.begin();
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}
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storeQueue.push_front(entry);
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SQItHash[store_index] = storeQueue.begin();
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++stores;
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}
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template <class Impl>
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typename Impl::DynInstPtr
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OzoneLWLSQ<Impl>::getMemDepViolator()
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{
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DynInstPtr temp = memDepViolator;
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memDepViolator = NULL;
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return temp;
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}
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template <class Impl>
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unsigned
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OzoneLWLSQ<Impl>::numFreeEntries()
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{
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unsigned free_lq_entries = LQEntries - loads;
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unsigned free_sq_entries = SQEntries - stores;
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// Both the LQ and SQ entries have an extra dummy entry to differentiate
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// empty/full conditions. Subtract 1 from the free entries.
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if (free_lq_entries < free_sq_entries) {
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return free_lq_entries - 1;
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} else {
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return free_sq_entries - 1;
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}
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}
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template <class Impl>
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int
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OzoneLWLSQ<Impl>::numLoadsReady()
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{
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int retval = 0;
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LQIt lq_it = loadQueue.begin();
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LQIt end_it = loadQueue.end();
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while (lq_it != end_it) {
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if ((*lq_it)->readyToIssue()) {
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++retval;
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}
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}
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return retval;
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}
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template <class Impl>
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Fault
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OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
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{
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// Execute a specific load.
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Fault load_fault = NoFault;
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DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
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inst->readPC(),inst->seqNum);
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// Make sure it's really in the list.
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// Normally it should always be in the list. However,
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/* due to a syscall it may not be the list.
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#ifdef DEBUG
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int i = loadHead;
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while (1) {
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if (i == loadTail && !find(inst)) {
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assert(0 && "Load not in the queue!");
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} else if (loadQueue[i] == inst) {
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break;
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}
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i = i + 1;
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if (i >= LQEntries) {
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i = 0;
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}
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}
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#endif // DEBUG*/
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load_fault = inst->initiateAcc();
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// Might want to make sure that I'm not overwriting a previously faulting
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// instruction that hasn't been checked yet.
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// Actually probably want the oldest faulting load
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if (load_fault != NoFault) {
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DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
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// Maybe just set it as can commit here, although that might cause
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// some other problems with sending traps to the ROB too quickly.
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be->instToCommit(inst);
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// iewStage->activityThisCycle();
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}
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return load_fault;
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}
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template <class Impl>
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Fault
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OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
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{
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// Make sure that a store exists.
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assert(stores != 0);
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int store_idx = store_inst->sqIdx;
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SQHashIt sq_hash_it = SQItHash.find(store_idx);
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assert(sq_hash_it != SQItHash.end());
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DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
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store_inst->readPC(), store_inst->seqNum);
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SQIt sq_it = (*sq_hash_it).second;
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Fault store_fault = store_inst->initiateAcc();
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// Store size should now be available. Use it to get proper offset for
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// addr comparisons.
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int size = (*sq_it).size;
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if (size == 0) {
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DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
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store_inst->readPC(),store_inst->seqNum);
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return store_fault;
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}
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assert(store_fault == NoFault);
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if (!storeFaultInst) {
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if (store_fault != NoFault) {
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panic("Fault in a store instruction!");
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storeFaultInst = store_inst;
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} else if (store_inst->isNonSpeculative()) {
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// Nonspeculative accesses (namely store conditionals)
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// need to set themselves as able to writeback if we
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// haven't had a fault by here.
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(*sq_it).canWB = true;
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++storesToWB;
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DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
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storesToWB);
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}
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}
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LQIt lq_it = --(loadQueue.end());
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if (!memDepViolator) {
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while (lq_it != loadQueue.end()) {
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if ((*lq_it)->seqNum < store_inst->seqNum) {
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lq_it--;
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continue;
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}
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// Actually should only check loads that have actually executed
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// Might be safe because effAddr is set to InvalAddr when the
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// dyn inst is created.
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// Must actually check all addrs in the proper size range
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// Which is more correct than needs to be. What if for now we just
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// assume all loads are quad-word loads, and do the addr based
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// on that.
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// @todo: Fix this, magic number being used here
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if (((*lq_it)->effAddr >> 8) ==
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(store_inst->effAddr >> 8)) {
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// A load incorrectly passed this store. Squash and refetch.
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// For now return a fault to show that it was unsuccessful.
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memDepViolator = (*lq_it);
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return TheISA::genMachineCheckFault();
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}
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lq_it--;
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}
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// If we've reached this point, there was no violation.
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memDepViolator = NULL;
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}
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return store_fault;
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::commitLoad()
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{
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assert(!loadQueue.empty());
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DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
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loadQueue.back()->seqNum, loadQueue.back()->readPC());
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LQIndices.push(loadQueue.back()->lqIdx);
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LQItHash.erase(loadQueue.back()->lqIdx);
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loadQueue.pop_back();
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--loads;
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
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{
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assert(loads == 0 || !loadQueue.empty());
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while (loads != 0 &&
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loadQueue.back()->seqNum <= youngest_inst) {
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commitLoad();
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}
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
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{
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assert(stores == 0 || !storeQueue.empty());
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SQIt sq_it = --(storeQueue.end());
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while (!storeQueue.empty() && sq_it != storeQueue.end()) {
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assert((*sq_it).inst);
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if (!(*sq_it).canWB) {
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if ((*sq_it).inst->seqNum > youngest_inst) {
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break;
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}
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++storesToWB;
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DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
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"%#x [sn:%lli], storesToWB:%i\n",
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(*sq_it).inst->readPC(),
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(*sq_it).inst->seqNum,
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storesToWB);
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(*sq_it).canWB = true;
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}
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sq_it--;
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}
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}
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template <class Impl>
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void
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OzoneLWLSQ<Impl>::writebackStores()
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{
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SQIt sq_it = --(storeQueue.end());
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while (storesToWB > 0 &&
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sq_it != storeQueue.end() &&
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(*sq_it).inst &&
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(*sq_it).canWB &&
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usedPorts < cachePorts) {
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DynInstPtr inst = (*sq_it).inst;
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if ((*sq_it).size == 0 && !(*sq_it).completed) {
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sq_it--;
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completeStore(inst->sqIdx);
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continue;
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}
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if (inst->isDataPrefetch() || (*sq_it).committed) {
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sq_it--;
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continue;
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}
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if (dcacheInterface && dcacheInterface->isBlocked()) {
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DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
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" is blocked!\n");
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break;
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}
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++usedPorts;
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assert((*sq_it).req);
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assert(!(*sq_it).committed);
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MemReqPtr req = (*sq_it).req;
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(*sq_it).committed = true;
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req->cmd = Write;
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req->completionEvent = NULL;
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req->time = curTick;
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assert(!req->data);
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req->data = new uint8_t[64];
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memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
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DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
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"to Addr:%#x, data:%#x [sn:%lli]\n",
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inst->sqIdx,inst->readPC(),
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req->paddr, *(req->data),
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inst->seqNum);
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if (dcacheInterface) {
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MemAccessResult result = dcacheInterface->access(req);
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if (isStalled() &&
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inst->seqNum == stallingStoreIsn) {
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DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
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"load [sn:%lli]\n",
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stallingStoreIsn, (*stallingLoad)->seqNum);
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stalled = false;
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stallingStoreIsn = 0;
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be->replayMemInst((*stallingLoad));
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}
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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// Event *wb = NULL;
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typename BackEnd::LdWritebackEvent *wb = NULL;
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if (req->flags & LOCKED) {
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// Stx_C does not generate a system port transaction.
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req->result=1;
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wb = new typename BackEnd::LdWritebackEvent(inst,
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be);
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}
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DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
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// DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
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// inst->seqNum);
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// Will stores need their own kind of writeback events?
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// Do stores even need writeback events?
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assert(!req->completionEvent);
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req->completionEvent = new
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StoreCompletionEvent(inst, be, wb, this);
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|
be->addDcacheMiss(inst);
|
|
|
|
lastDcacheStall = curTick;
|
|
|
|
_status = DcacheMissStall;
|
|
|
|
// Increment stat here or something
|
|
|
|
sq_it--;
|
|
} else {
|
|
DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
|
|
inst->sqIdx);
|
|
|
|
// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
|
|
// inst->seqNum);
|
|
|
|
if (req->flags & LOCKED) {
|
|
// Stx_C does not generate a system port transaction.
|
|
if (req->flags & UNCACHEABLE) {
|
|
req->result = 2;
|
|
} else {
|
|
req->result = 1;
|
|
}
|
|
|
|
typename BackEnd::LdWritebackEvent *wb =
|
|
new typename BackEnd::LdWritebackEvent(inst,
|
|
be);
|
|
wb->schedule(curTick);
|
|
}
|
|
sq_it--;
|
|
completeStore(inst->sqIdx);
|
|
}
|
|
} else {
|
|
panic("Must HAVE DCACHE!!!!!\n");
|
|
}
|
|
}
|
|
|
|
// Not sure this should set it to 0.
|
|
usedPorts = 0;
|
|
|
|
assert(stores >= 0 && storesToWB >= 0);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
|
|
{
|
|
DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
|
|
"(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
|
|
|
|
|
|
LQIt lq_it = loadQueue.begin();
|
|
|
|
while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
|
|
assert(!loadQueue.empty());
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
|
|
"[sn:%lli]\n",
|
|
(*lq_it)->readPC(),
|
|
(*lq_it)->seqNum);
|
|
|
|
if (isStalled() && lq_it == stallingLoad) {
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
stallingLoad = NULL;
|
|
}
|
|
|
|
--loads;
|
|
|
|
// Inefficient!
|
|
LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
|
|
assert(lq_hash_it != LQItHash.end());
|
|
LQItHash.erase(lq_hash_it);
|
|
LQIndices.push((*lq_it)->lqIdx);
|
|
loadQueue.erase(lq_it++);
|
|
}
|
|
|
|
if (isLoadBlocked) {
|
|
if (squashed_num < blockedLoadSeqNum) {
|
|
isLoadBlocked = false;
|
|
loadBlockedHandled = false;
|
|
blockedLoadSeqNum = 0;
|
|
}
|
|
}
|
|
|
|
SQIt sq_it = storeQueue.begin();
|
|
|
|
while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
|
|
assert(!storeQueue.empty());
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
|
|
(*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
|
|
(*sq_it).inst->seqNum);
|
|
|
|
// I don't think this can happen. It should have been cleared by the
|
|
// stalling load.
|
|
if (isStalled() &&
|
|
(*sq_it).inst->seqNum == stallingStoreIsn) {
|
|
panic("Is stalled should have been cleared by stalling load!\n");
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
}
|
|
|
|
SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
|
|
assert(sq_hash_it != SQItHash.end());
|
|
SQItHash.erase(sq_hash_it);
|
|
SQIndices.push((*sq_it).inst->sqIdx);
|
|
(*sq_it).inst = NULL;
|
|
(*sq_it).canWB = 0;
|
|
|
|
if ((*sq_it).req) {
|
|
assert(!(*sq_it).req->completionEvent);
|
|
}
|
|
(*sq_it).req = NULL;
|
|
--stores;
|
|
storeQueue.erase(sq_it++);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneLWLSQ<Impl>::dumpInsts()
|
|
{
|
|
cprintf("Load store queue: Dumping instructions.\n");
|
|
cprintf("Load queue size: %i\n", loads);
|
|
cprintf("Load queue: ");
|
|
|
|
LQIt lq_it = --(loadQueue.end());
|
|
|
|
while (lq_it != loadQueue.end() && (*lq_it)) {
|
|
cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
|
|
(*lq_it)->readPC());
|
|
|
|
lq_it--;
|
|
}
|
|
|
|
cprintf("\nStore queue size: %i\n", stores);
|
|
cprintf("Store queue: ");
|
|
|
|
SQIt sq_it = --(storeQueue.end());
|
|
|
|
while (sq_it != storeQueue.end() && (*sq_it).inst) {
|
|
cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
|
|
(*sq_it).inst->seqNum,
|
|
(*sq_it).inst->readPC(),
|
|
(*sq_it).size,
|
|
(*sq_it).committed,
|
|
(*sq_it).completed,
|
|
(*sq_it).canWB);
|
|
|
|
sq_it--;
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
OzoneLWLSQ<Impl>::completeStore(int store_idx)
|
|
{
|
|
SQHashIt sq_hash_it = SQItHash.find(store_idx);
|
|
assert(sq_hash_it != SQItHash.end());
|
|
SQIt sq_it = (*sq_hash_it).second;
|
|
|
|
assert((*sq_it).inst);
|
|
(*sq_it).completed = true;
|
|
DynInstPtr inst = (*sq_it).inst;
|
|
|
|
--storesToWB;
|
|
|
|
if (isStalled() &&
|
|
inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
|
|
"load [sn:%lli]\n",
|
|
stallingStoreIsn, (*stallingLoad)->seqNum);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
be->replayMemInst((*stallingLoad));
|
|
}
|
|
|
|
DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
|
|
inst->sqIdx, inst->seqNum, storesToWB);
|
|
|
|
// A bit conservative because a store completion may not free up entries,
|
|
// but hopefully avoids two store completions in one cycle from making
|
|
// the CPU tick twice.
|
|
// cpu->activityThisCycle();
|
|
assert(!storeQueue.empty());
|
|
SQItHash.erase(sq_hash_it);
|
|
SQIndices.push(inst->sqIdx);
|
|
storeQueue.erase(sq_it);
|
|
--stores;
|
|
/*
|
|
SQIt oldest_store_it = --(storeQueue.end());
|
|
if (sq_it == oldest_store_it) {
|
|
do {
|
|
inst = (*oldest_store_it).inst;
|
|
sq_hash_it = SQItHash.find(inst->sqIdx);
|
|
assert(sq_hash_it != SQItHash.end());
|
|
SQItHash.erase(sq_hash_it);
|
|
SQIndices.push(inst->sqIdx);
|
|
storeQueue.erase(oldest_store_it--);
|
|
|
|
--stores;
|
|
} while ((*oldest_store_it).completed &&
|
|
oldest_store_it != storeQueue.end());
|
|
|
|
// be->updateLSQNextCycle = true;
|
|
}
|
|
*/
|
|
}
|