c1aecc05e6
This patch extensively modifies DSENT so that it can be accessed using Python. To access the Python interface, DSENT needs to compiled as a shared library. For this purpose a CMakeLists.txt file has been added. Some of the code that is not required is being removed.
222 lines
9.3 KiB
C++
222 lines
9.3 KiB
C++
/* Copyright (c) 2012 Massachusetts Institute of Technology
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "model/electrical/router/RouterInputPort.h"
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#include <cmath>
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#include <vector>
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#include "model/PortInfo.h"
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#include "model/EventInfo.h"
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#include "model/TransitionInfo.h"
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#include "model/ModelGen.h"
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#include "model/std_cells/StdCellLib.h"
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#include "model/std_cells/StdCell.h"
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namespace DSENT
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{
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using std::ceil;
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using std::vector;
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using LibUtil::castStringVector;
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RouterInputPort::RouterInputPort(const String& instance_name_, const TechModel* tech_model_)
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: ElectricalModel(instance_name_, tech_model_)
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{
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initParameters();
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initProperties();
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}
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RouterInputPort::~RouterInputPort()
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{}
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void RouterInputPort::initParameters()
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{
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addParameterName("NumberVirtualNetworks");
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addParameterName("NumberVirtualChannelsPerVirtualNetwork");
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addParameterName("NumberBuffersPerVirtualChannel");
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addParameterName("NumberBitsPerFlit");
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addParameterName("BufferModel");
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return;
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}
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void RouterInputPort::initProperties()
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{
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return;
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}
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RouterInputPort* RouterInputPort::clone() const
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{
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// TODO
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return NULL;
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}
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void RouterInputPort::constructModel()
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{
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// Get parameters
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unsigned int number_vns = getParameter("NumberVirtualNetworks").toUInt();
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const vector<unsigned int>& number_vcs_per_vn_vector = castStringVector<unsigned int>(getParameter("NumberVirtualChannelsPerVirtualNetwork").split("[,]"));
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const vector<unsigned int>& number_bufs_per_vc_vector = castStringVector<unsigned int>(getParameter("NumberBuffersPerVirtualChannel").split("[,]"));
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unsigned int number_bits_per_flit = getParameter("NumberBitsPerFlit").toUInt();
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const String& buffer_model = getParameter("BufferModel");
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ASSERT(number_vns > 0, "[Error] " + getInstanceName() +
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" -> Number of virtual networks must be > 0!");
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ASSERT(number_vcs_per_vn_vector.size() == number_vns, "[Error] " + getInstanceName() +
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" -> Expecting " + (String)number_vns + " number of vcs, got " +
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getParameter("NumberVirtualChannelsPerVirtualNetwork"));
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for(unsigned int i = 0; i < number_vns; ++i)
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{
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ASSERT(number_vcs_per_vn_vector[i] > 0, "[Error] " + getInstanceName() +
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" -> Number of virtual channels per virtual network must be > 0!");
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}
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ASSERT(number_bufs_per_vc_vector.size() == number_vns, "[Error] " + getInstanceName() +
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" -> Expecting " + (String)number_vns + " number of bufs per vc, got " +
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getParameter("NumberBuffersPerVirtualChannel"));
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for(unsigned int i = 0; i < number_vns; ++i)
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{
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ASSERT(number_bufs_per_vc_vector[i] > 0, "[Error] " + getInstanceName() +
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" -> Number of buffers per virtual channel must be > 0!");
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}
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ASSERT(number_bits_per_flit > 0, "[Error] " + getInstanceName() +
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" -> Number of bits per buffer must be > 0!");
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// Calculate total number of buffers needed in the RAM
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unsigned int total_number_vcs = 0;
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unsigned int total_number_bufs = 0;
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for(unsigned int i = 0; i < number_vns; ++i)
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{
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total_number_vcs += number_vcs_per_vn_vector[i];
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total_number_bufs += number_vcs_per_vn_vector[i] * number_bufs_per_vc_vector[i];
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}
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unsigned int number_addr_bits = (unsigned int)ceil(log2(total_number_bufs));
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getGenProperties()->set("TotalNumberVirtualChannels", total_number_vcs);
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getGenProperties()->set("TotalNumberBuffers", total_number_bufs);
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getGenProperties()->set("NumberAddressBits", number_addr_bits);
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getGenProperties()->set("NumberOutputs", 1);
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createInputPort("CK");
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createInputPort("FlitIn", makeNetIndex(0, number_bits_per_flit-1));
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createOutputPort("FlitOut", makeNetIndex(0, number_bits_per_flit-1));
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// Create energy, power, and area results
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createElectricalResults();
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getEventInfo("Idle")->setStaticTransitionInfos();
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getEventInfo("Idle")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
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addEventResult(new Result("ReadBuffer"));
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addEventResult(new Result("WriteBuffer"));
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// Init RAM
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const String& ram_name = "RAM";
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ElectricalModel* ram = ModelGen::createRAM(buffer_model, ram_name, getTechModel());
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ram->setParameter("NumberEntries", total_number_bufs);
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ram->setParameter("NumberBits", number_bits_per_flit);
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ram->construct();
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// Init DFF for read address
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vector<String> rd_addr_dff_names(number_addr_bits, "");
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vector<StdCell*> rd_addr_dffs(number_addr_bits, NULL);
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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rd_addr_dff_names[i] = "RDAddr_DFF" + (String)i;
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rd_addr_dffs[i] = getTechModel()->getStdCellLib()->createStdCell("DFFQ", rd_addr_dff_names[i]);
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rd_addr_dffs[i]->construct();
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}
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// Connect RDAddr_DFFs
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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createNet("RDAddr_DFF_Out" + (String)i);
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portConnect(rd_addr_dffs[i], "CK", "CK");
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portConnect(rd_addr_dffs[i], "Q", "RDAddr_DFF_Out" + (String)i);
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}
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// Connect RAM
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portConnect(ram, "In", "FlitIn");
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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portConnect(ram, "WRAddr" + (String)i, "FlitIn", makeNetIndex(i));
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portConnect(ram, "RDAddr" + (String)i, "RDAddr_DFF_Out" + (String)i);
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}
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portConnect(ram, "WE", "FlitIn", makeNetIndex(number_bits_per_flit-1));
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portConnect(ram, "CK", "CK");
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portConnect(ram, "Out", "FlitOut");
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// Add area, power, event results
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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addSubInstances(rd_addr_dffs[i], number_addr_bits);
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addElectricalSubResults(rd_addr_dffs[i], number_addr_bits);
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}
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addSubInstances(ram, 1.0);
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addElectricalSubResults(ram, 1.0);
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getEventResult("WriteBuffer")->addSubResult(ram->getEventResult("Write"), ram_name, 1.0);
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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getEventResult("ReadBuffer")->addSubResult(rd_addr_dffs[i]->getEventResult("DFFD"), rd_addr_dff_names[i], number_addr_bits);
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getEventResult("ReadBuffer")->addSubResult(rd_addr_dffs[i]->getEventResult("DFFQ"), rd_addr_dff_names[i], number_addr_bits);
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getEventResult("ReadBuffer")->addSubResult(rd_addr_dffs[i]->getEventResult("CK"), rd_addr_dff_names[i], number_addr_bits);
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}
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getEventResult("ReadBuffer")->addSubResult(ram->getEventResult("Read"), ram_name, 1.0);
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return;
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}
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void RouterInputPort::propagateTransitionInfo()
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{
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// Update probability and activity
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unsigned int number_addr_bits = getGenProperties()->get("NumberAddressBits").toUInt();
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vector<ElectricalModel*> rd_addr_dffs(number_addr_bits, NULL);
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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rd_addr_dffs[i] = (ElectricalModel*)getSubInstance("RDAddr_DFF" + (String)i);
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assignPortTransitionInfo(rd_addr_dffs[i], "D", TransitionInfo());
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propagatePortTransitionInfo(rd_addr_dffs[i], "CK", "CK");
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rd_addr_dffs[i]->use();
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}
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ElectricalModel* ram = (ElectricalModel*)getSubInstance("RAM");
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// Setup default transition info
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const String& current_event = getGenProperties()->get("UseModelEvent");
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if(current_event != "Idle")
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{
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propagatePortTransitionInfo(ram, "In", "FlitIn");
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propagatePortTransitionInfo(ram, "CK", "CK");
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assignPortTransitionInfo(ram, "WE", TransitionInfo(0.0, 0.0, 1.0));
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for(unsigned int i = 0; i < number_addr_bits; ++i)
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{
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assignPortTransitionInfo(ram, "WRAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25));
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assignPortTransitionInfo(ram, "RDAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25));
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}
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}
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ram->use();
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// Set output probability
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propagatePortTransitionInfo("FlitOut", ram, "Out");
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return;
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}
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} // namespace DSENT
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