387 lines
16 KiB
C
387 lines
16 KiB
C
/*
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* Copyright (c) 1990 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Keith Bostic, Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Defines for the architected startup addresses.
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*/
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#define HWRPB_ADDR 0x10000000 /* 256 MB */
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#define BOOT_ADDR 0x20000000 /* 512 MB */
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#define PGTBL_ADDR 0x40000000 /* 1 GB */
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/*
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* Values for the "haltcode" field in the per-cpu portion of the HWRPB
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*
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* Bit defines for the "sysvar" field in the HWRPB.
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* Each platform has different values for SYSBOARD and IOBOARD bits.
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*/
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#define HALT_PWRUP 0 /* power up */
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#define HALT_OPR 1 /* operator issued halt cmd */
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#define HALT_KSTK 2 /* kernel stack not valid */
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#define HALT_SCBB 3 /* invalid SCBB */
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#define HALT_PTBR 4 /* invalid PTBR */
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#define HALT_EXE 5 /* kernel executed halt instruction */
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#define HALT_DBLE 6 /* double error abort */
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/*
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* Bit defines for the "state" field in the per-cpu portion of the HWRPB
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*/
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#define STATE_BIP 0x00000001 /* bootstrap in progress */
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#define STATE_RC 0x00000002 /* restart capable */
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#define STATE_PA 0x00000004 /* processor available to OS */
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#define STATE_PP 0x00000008 /* processor present */
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#define STATE_OH 0x00000010 /* operator halted */
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#define STATE_CV 0x00000020 /* context valid */
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#define STATE_PV 0x00000040 /* PALcode valid */
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#define STATE_PMV 0x00000080 /* PALcode memory valid */
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#define STATE_PL 0x00000100 /* PALcode loaded */
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#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */
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#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */
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#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */
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#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */
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#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */
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#define STATE_HALT 0x00040000 /* Remain halted (no restart) */
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#define SV_PF_RSVD 0x00000000 /* RESERVED */
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#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */
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#define SV_MPCAP 0x00000001 /* MP capable */
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#define SV_PF_UNITED 0x00000020 /* United */
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#define SV_PF_SEPARATE 0x00000040 /* Separate */
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#define SV_PF_FULLBB 0x00000060 /* Full battery backup */
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#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */
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#define SV_PF_RESTART 0x00000100 /* Powerfail restart */
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#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */
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#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */
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#define SV_SANDPIPER 0x00000400 /* others define system platforms */
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#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */
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#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */
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#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */
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#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */
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#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */
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#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */
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#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */
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#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */
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#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */
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/*
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* Values for the "console type" field in the CTB portion of the HWRPB
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*/
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#define CONS_NONE 0 /* no console present */
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#define CONS_SRVC 1 /* console is service processor */
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#define CONS_DZ 2 /* console is dz/dl VT device */
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#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/
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#define CONS_REM 4 /* cons is remote, protocal enet/MOP */
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/*
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* PALcode variants that we're interested in.
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* Used as indices into the "palrev_avail" array in the per-cpu portion
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* of the HWRPB.
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*/
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#define PALvar_reserved 0
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#define PALvar_OpenVMS 1
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#define PALvar_OSF1 2
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/*
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* The Alpha restart parameter block, which is a page or 2 in low memory
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*/
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struct rpb {
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struct rpb *rpb_selfref; /* 000: physical self-reference */
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long rpb_string; /* 008: contains string "HWRPB" */
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long rpb_vers; /* 010: HWRPB version number */
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ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
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ulong rpb_cpuid; /* 020: primary cpu id */
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ulong rpb_pagesize; /* 028: page size in bytes */
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ulong rpb_addrbits; /* 030: number of phys addr bits */
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ulong rpb_maxasn; /* 038: max valid ASN */
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char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */
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ulong grpb_systype; /* 050: system type */
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long rpb_sysvar; /* 058: system variation */
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long rpb_sysrev; /* 060: system revision */
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ulong rpb_clock; /* 068: scaled interval clock intr freq */
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ulong rpb_counter; /* 070: cycle counter frequency */
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ulong rpb_vptb; /* 078: virtual page table base */
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long rpb_res1; /* 080: reserved */
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ulong rpb_trans_off; /* 088: offset to translation buffer hint */
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ulong rpb_numprocs; /* 090: number of processor slots */
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ulong rpb_slotsize; /* 098: per-cpu slot size */
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ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */
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ulong rpb_num_ctb; /* 0A8: number of CTBs */
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ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */
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ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */
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ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */
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ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */
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ulong rpb_config_off; /* 0D0: offset to config data block */
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ulong rpb_fru_off; /* 0D8: offset to FRU table */
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void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */
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long rpb_saveterm_pv; /* 0E8: proc value for save term routine */
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void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */
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long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */
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void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */
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long rpb_restart_pv; /* 108: proc value for CPU restart routine */
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long rpb_software; /* 110: used to determine presence of kdebug */
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long rpb_hardware; /* 118: reserved for hardware */
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long rpb_checksum; /* 120: checksum of prior entries in rpb */
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long rpb_rxrdy; /* 128: receive ready bitmask */
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long rpb_txrdy; /* 130: transmit ready bitmask */
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ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */
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};
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#define rpb_kdebug rpb_software
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#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23))
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/*
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* This is the format for the boot/restart HWPCB. It must match the
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* initial fields of the pcb structure as defined in pcb.h, but must
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* additionally contain the appropriate amount of padding to line up
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* with formats used by other palcode types.
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*/
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struct bootpcb {
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long rpb_ksp; /* 000: kernel stack pointer */
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long rpb_usp; /* 008: user stack pointer */
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long rpb_ptbr; /* 010: page table base register */
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int rpb_cc; /* 018: cycle counter */
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int rpb_asn; /* 01C: address space number */
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long rpb_proc_uniq; /* 020: proc/thread unique value */
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long rpb_fen; /* 028: floating point enable */
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long rpb_palscr[2]; /* 030: pal scratch area */
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long rpb_pcbpad[8]; /* 040: padding for fixed size */
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};
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/*
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* Inter-Console Communications Buffer
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* Used for the primary processor to communcate with the console
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* of secondary processors.
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*/
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struct iccb {
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uint iccb_rxlen; /* receive length in bytes */
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uint iccb_txlen; /* transmit length in bytes */
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char iccb_rxbuf[80]; /* receive buffer */
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char iccb_txbuf[80]; /* transmit buffer */
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};
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/*
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* The per-cpu portion of the Alpha HWRPB.
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* Note that the main portion of the HWRPB is of variable size,
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* hence this must be a separate structure.
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*
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*/
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struct rpb_percpu {
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struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */
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long rpb_state; /* 080: per-cpu state bits */
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long rpb_palmem; /* 088: palcode memory length */
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long rpb_palscratch; /* 090: palcode scratch length */
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long rpb_palmem_addr; /* 098: phys addr of palcode mem space */
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long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */
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long rpb_palrev; /* 0A8: PALcode rev required */
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long rpb_proctype; /* 0B0: processor type */
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long rpb_procvar; /* 0B8: processor variation */
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long rpb_procrev; /* 0C0: processor revision */
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char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */
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long rpb_logout; /* 0D8: phys addr of logout area */
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long rpb_logout_len; /* 0E0: length in bytes of logout area */
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long rpb_haltpb; /* 0E8: halt pcb base */
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long rpb_haltpc; /* 0F0: halt pc */
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long rpb_haltps; /* 0F8: halt ps */
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long rpb_haltal; /* 100: halt arg list (R25) */
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long rpb_haltra; /* 108: halt return address (R26) */
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long rpb_haltpv; /* 110: halt procedure value (R27) */
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long rpb_haltcode; /* 118: reason for halt */
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long rpb_software; /* 120: for software */
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struct iccb rpb_iccb; /* 128: inter-console communications buffer */
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long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */
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long rpb_pcrsvd[6]; /* 250: reserved for arch use */
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/* the dump stack grows from the end of the rpb page not to reach here */
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};
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/* The firmware revision is in the (unused) first entry of palrevs available */
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#define rpb_firmrev rpb_palrev_avail[0]
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/*
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* The memory cluster descriptor.
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*/
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struct rpb_cluster {
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long rpb_pfn; /* 000: starting PFN of this cluster */
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long rpb_pfncount; /* 008: count of PFNs in this cluster */
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long rpb_pfntested; /* 010: count of tested PFNs in cluster */
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long rpb_va; /* 018: va of bitmap */
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long rpb_pa; /* 020: pa of bitmap */
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long rpb_checksum; /* 028: checksum of bitmap */
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long rpb_usage; /* 030: usage of cluster */
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};
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#define CLUSTER_USAGE_OS ((long)0)
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#define CLUSTER_USAGE_PAL ((long)1)
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#define CLUSTER_USAGE_NVRAM ((long)2)
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/*
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* The "memory descriptor table" portion of the HWRPB.
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* Note that the main portion of the HWRPB is of variable size and there is a
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* variable number of per-cpu slots, hence this must be a separate structure.
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* Also note that the memory descriptor table contains a fixed portion plus
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* a variable number of "memory cluster descriptors" (one for each "cluster"
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* of memory).
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*/
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struct rpb_mdt {
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long rpb_checksum; /* 000: checksum of entire mem desc table */
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long rpb_impaddr; /* 008: PA of implementation dep info */
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long rpb_numcl; /* 010: number of clusters */
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struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */
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};
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/*
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* The "Console Terminal Block" portion of the HWRPB, for serial line
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* UART console device.
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*/
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struct ctb_tt {
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long ctb_type; /* 0: always 4 */
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long ctb_unit; /* 8: */
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long ctb_reserved; /* 16: */
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long ctb_len; /* 24: bytes of info */
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long ctb_ipl; /* 32: console ipl level */
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long ctb_tintr_vec; /* 40: transmit vec (0x800) */
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long ctb_rintr_vec; /* 48: receive vec (0x800) */
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#define CTB_GRAPHICS 3 /* graphics device */
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#define CTB_NETWORK 0xC0 /* network device */
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#define CTB_PRINTERPORT 2 /* printer port on the SCC */
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long ctb_term_type; /* 56: terminal type */
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long ctb_keybd_type; /* 64: keyboard nationality */
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long ctb_keybd_trans; /* 72: trans. table addr */
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long ctb_keybd_map; /* 80: map table addr */
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long ctb_keybd_state; /* 88: keyboard flags */
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long ctb_keybd_last; /* 96: last key entered */
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long ctb_font_us; /* 104: US font table addr */
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long ctb_font_mcs; /* 112: MCS font table addr */
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long ctb_font_width; /* 120: font width, height */
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long ctb_font_height; /* 128: in pixels */
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long ctb_mon_width; /* 136: monitor width, height */
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long ctb_mon_height; /* 144: in pixels */
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long ctb_dpi; /* 152: monitor dots per inch */
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long ctb_planes; /* 160: # of planes */
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long ctb_cur_width; /* 168: cursor width, height */
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long ctb_cur_height; /* 176: in pixels */
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long ctb_head_cnt; /* 184: # of heads */
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long ctb_opwindow; /* 192: opwindow on screen */
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long ctb_head_offset; /* 200: offset to head info */
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long ctb_putchar; /* 208: output char to TURBO */
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long ctb_io_state; /* 216: I/O flags */
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long ctb_listen_state; /* 224: listener flags */
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long ctb_xaddr; /* 232: extended info addr */
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long ctb_turboslot; /* 248: TURBOchannel slot # */
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long ctb_server_off; /* 256: offset to server info */
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long ctb_line_off; /* 264: line parameter offset */
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char ctb_csd; /* 272: console specific data */
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};
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/*
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* The "Console Terminal Block" portion of the HWRPB.
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*/
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struct rpb_ctb {
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long rpb_type; /* 000: console type */
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long rpb_unit; /* 008: console unit */
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long rpb_resv; /* 010: reserved */
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long rpb_length; /* 018: byte length of device dep portion */
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long rpb_first; /* 000: first field of device dep portion */
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};
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/*
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* The physical/virtual map for the console routine block.
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*/
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struct rpb_map {
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long rpb_virt; /* virtual address for map entry */
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long rpb_phys; /* phys address for map entry */
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long rpb_pgcount; /* page count for map entry */
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};
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/*
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* The "Console Routine Block" portion of the HWRPB.
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* Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
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*/
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struct rpb_crb {
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long rpb_va_disp; /* va of call-back dispatch rtn */
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long rpb_pa_disp; /* pa of call-back dispatch rtn */
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long rpb_va_fixup; /* va of call-back fixup rtn */
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long rpb_pa_fixup; /* pa of call-back fixup rtn */
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long rpb_num; /* number of entries in phys/virt map */
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long rpb_mapped_pages; /* Number of pages to be mapped */
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struct rpb_map rpb_map[1]; /* first instance of a map entry */
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};
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/*
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* These macros define where within the HWRPB the CTB and CRB are located.
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*/
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#define CTB_SETUP \
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((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off)))
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#define CRB_SETUP \
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((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off)))
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/*
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* The "Dynamic System Recognition" portion of the HWRPB.
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* It is used to obtain the platform specific data need to allow
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* the platform define the platform name, the platform SMM and LURT
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* data for software licensing
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*/
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struct rpb_dsr {
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long rpb_smm; /* SMM nubber used by LMF */
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ulong rpb_lurt_off; /* offset to LURT table */
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ulong rpb_sysname_off; /* offset to sysname char count */
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int lurt[10]; /* XXM has one LURT entry */
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};
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