b00949d88b
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
80 lines
3.6 KiB
Python
80 lines
3.6 KiB
Python
# Copyright (c) 2005-2007 The Regents of The University of Michigan
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# Copyright (c) 2011 Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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# Rick Strong
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from m5.SimObject import SimObject
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from m5.defines import buildEnv
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from m5.params import *
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from m5.proxy import *
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from SimpleMemory import *
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class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
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class System(MemObject):
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type = 'System'
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system_port = MasterPort("System port")
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@classmethod
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def export_method_cxx_predecls(cls, code):
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code('#include "sim/system.hh"')
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@classmethod
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def export_methods(cls, code):
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code('''
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Enums::MemoryMode getMemoryMode();
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void setMemoryMode(Enums::MemoryMode mode);
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''')
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memories = VectorParam.AbstractMemory(Self.all,
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"All memories in the system")
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mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
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work_item_id = Param.Int(-1, "specific work item id")
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num_work_ids = Param.Int(16, "Number of distinct work item types")
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work_begin_cpu_id_exit = Param.Int(-1,
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"work started on specific id, now exit simulation")
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work_begin_ckpt_count = Param.Counter(0,
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"create checkpoint when work items begin count value is reached")
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work_begin_exit_count = Param.Counter(0,
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"exit simulation when work items begin count value is reached")
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work_end_ckpt_count = Param.Counter(0,
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"create checkpoint when work items end count value is reached")
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work_end_exit_count = Param.Counter(0,
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"exit simulation when work items end count value is reached")
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work_cpus_ckpt_count = Param.Counter(0,
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"create checkpoint when active cpu count value is reached")
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init_param = Param.UInt64(0, "numerical value to pass into simulator")
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boot_osflags = Param.String("a", "boot flags to pass to the kernel")
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kernel = Param.String("", "file that contains the kernel code")
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readfile = Param.String("", "file to read startup script from")
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symbolfile = Param.String("", "file to get the symbols from")
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load_addr_mask = Param.UInt64(0xffffffffff,
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"Address to mask loading binaries with");
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