af6aaf2581
Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification.
387 lines
11 KiB
C++
387 lines
11 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_TABLE_WALKER_HH__
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#define __ARCH_ARM_TABLE_WALKER_HH__
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#include <list>
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/tlb.hh"
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#include "mem/mem_object.hh"
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#include "mem/request.hh"
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#include "params/ArmTableWalker.hh"
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#include "sim/eventq.hh"
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#include "sim/fault_fwd.hh"
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class DmaPort;
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class ThreadContext;
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namespace ArmISA {
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class Translation;
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class TLB;
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class TableWalker : public MemObject
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{
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public:
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struct L1Descriptor {
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/** Type of page table entry ARM DDI 0406B: B3-8*/
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enum EntryType {
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Ignore,
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PageTable,
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Section,
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Reserved
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};
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/** The raw bits of the entry */
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uint32_t data;
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/** This entry has been modified (access flag set) and needs to be
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* written back to memory */
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bool _dirty;
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EntryType type() const
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{
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return (EntryType)(data & 0x3);
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}
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/** Is the page a Supersection (16MB)?*/
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bool supersection() const
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{
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return bits(data, 18);
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}
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/** Return the physcal address of the entry, bits in position*/
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Addr paddr() const
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{
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if (supersection())
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panic("Super sections not implemented\n");
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return mbits(data, 31, 20);
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}
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/** Return the physcal address of the entry, bits in position*/
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Addr paddr(Addr va) const
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{
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if (supersection())
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panic("Super sections not implemented\n");
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return mbits(data, 31, 20) | mbits(va, 19, 0);
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}
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/** Return the physical frame, bits shifted right */
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Addr pfn() const
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{
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if (supersection())
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panic("Super sections not implemented\n");
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return bits(data, 31, 20);
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}
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/** Is the translation global (no asid used)? */
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bool global() const
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{
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return bits(data, 17);
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}
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/** Is the translation not allow execution? */
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bool xn() const
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{
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return bits(data, 4);
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}
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/** Three bit access protection flags */
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uint8_t ap() const
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{
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return (bits(data, 15) << 2) | bits(data, 11, 10);
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}
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/** Domain Client/Manager: ARM DDI 0406B: B3-31 */
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uint8_t domain() const
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{
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return bits(data, 8, 5);
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}
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/** Address of L2 descriptor if it exists */
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Addr l2Addr() const
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{
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return mbits(data, 31, 10);
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}
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/** Memory region attributes: ARM DDI 0406B: B3-32.
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* These bits are largly ignored by M5 and only used to
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* provide the illusion that the memory system cares about
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* anything but cachable vs. uncachable.
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*/
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uint8_t texcb() const
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{
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return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
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}
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/** If the section is shareable. See texcb() comment. */
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bool shareable() const
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{
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return bits(data, 16);
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}
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/** Set access flag that this entry has been touched. Mark
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* the entry as requiring a writeback, in the future.
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*/
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void setAp0()
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{
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data |= 1 << 10;
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_dirty = true;
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}
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/** This entry needs to be written back to memory */
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bool dirty() const
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{
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return _dirty;
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}
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};
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/** Level 2 page table descriptor */
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struct L2Descriptor {
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/** The raw bits of the entry. */
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uint32_t data;
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/** This entry has been modified (access flag set) and needs to be
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* written back to memory */
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bool _dirty;
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/** Is the entry invalid */
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bool invalid() const
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{
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return bits(data, 1, 0) == 0;
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}
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/** What is the size of the mapping? */
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bool large() const
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{
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return bits(data, 1) == 0;
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}
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/** Is execution allowed on this mapping? */
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bool xn() const
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{
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return large() ? bits(data, 15) : bits(data, 0);
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}
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/** Is the translation global (no asid used)? */
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bool global() const
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{
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return !bits(data, 11);
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}
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/** Three bit access protection flags */
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uint8_t ap() const
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{
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return bits(data, 5, 4) | (bits(data, 9) << 2);
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}
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/** Memory region attributes: ARM DDI 0406B: B3-32 */
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uint8_t texcb() const
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{
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return large() ?
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(bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
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(bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
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}
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/** Return the physical frame, bits shifted right */
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Addr pfn() const
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{
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return large() ? bits(data, 31, 16) : bits(data, 31, 12);
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}
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/** Return complete physical address given a VA */
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Addr paddr(Addr va) const
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{
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if (large())
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return mbits(data, 31, 16) | mbits(va, 15, 0);
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else
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return mbits(data, 31, 12) | mbits(va, 11, 0);
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}
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/** If the section is shareable. See texcb() comment. */
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bool shareable() const
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{
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return bits(data, 10);
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}
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/** Set access flag that this entry has been touched. Mark
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* the entry as requiring a writeback, in the future.
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*/
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void setAp0()
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{
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data |= 1 << 4;
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_dirty = true;
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}
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/** This entry needs to be written back to memory */
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bool dirty() const
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{
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return _dirty;
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}
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};
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struct WalkerState //: public SimObject
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{
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/** Thread context that we're doing the walk for */
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ThreadContext *tc;
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/** Request that is currently being serviced */
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RequestPtr req;
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/** Context ID that we're servicing the request under */
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uint8_t contextId;
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/** Translation state for delayed requests */
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TLB::Translation *transState;
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/** The fault that we are going to return */
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Fault fault;
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/** The virtual address that is being translated */
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Addr vaddr;
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/** Cached copy of the sctlr as it existed when translation began */
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SCTLR sctlr;
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/** Width of the base address held in TTRB0 */
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uint32_t N;
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/** If the access is a write */
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bool isWrite;
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/** If the access is a fetch (for execution, and no-exec) must be checked?*/
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bool isFetch;
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/** If the mode is timing or atomic */
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bool timing;
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/** If the atomic mode should be functional */
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bool functional;
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/** Save mode for use in delayed response */
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BaseTLB::Mode mode;
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L1Descriptor l1Desc;
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L2Descriptor l2Desc;
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/** Whether L1/L2 descriptor response is delayed in timing mode */
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bool delayed;
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TableWalker *tableWalker;
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void doL1Descriptor();
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void doL2Descriptor();
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std::string name() const {return tableWalker->name();}
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};
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/** Queue of requests that need processing first level translation */
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std::list<WalkerState *> stateQueueL1;
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/** Queue of requests that have passed first level translation and
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* require an additional level. */
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std::list<WalkerState *> stateQueueL2;
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/** Queue of requests that have passed are waiting because the walker is
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* currently busy. */
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std::list<WalkerState *> pendingQueue;;
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/** Port to issue translation requests from */
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DmaPort *port;
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/** TLB that is initiating these table walks */
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TLB *tlb;
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/** Cached copy of the sctlr as it existed when translation began */
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SCTLR sctlr;
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WalkerState *currState;
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/** If a timing translation is currently in progress */
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bool pending;
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public:
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typedef ArmTableWalkerParams Params;
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TableWalker(const Params *p);
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virtual ~TableWalker();
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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virtual unsigned int drain(Event *de);
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virtual void resume();
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
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TLB::Translation *_trans, bool timing, bool functional = false);
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void setTlb(TLB *_tlb) { tlb = _tlb; }
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void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
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uint8_t texcb, bool s);
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private:
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void doL1Descriptor();
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void doL1DescriptorWrapper();
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EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
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void doL2Descriptor();
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void doL2DescriptorWrapper();
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EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
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Fault processWalk();
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void processWalkWrapper();
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EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
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void nextWalk(ThreadContext *tc);
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};
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} // namespace ArmISA
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#endif //__ARCH_ARM_TABLE_WALKER_HH__
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