9e45ada171
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
204 lines
22 KiB
Text
204 lines
22 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 255958 # Simulator instruction rate (inst/s)
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host_mem_usage 207264 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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host_tick_rate 701295215 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 15175 # Number of instructions simulated
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sim_seconds 0.000042 # Number of seconds simulated
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sim_ticks 41800000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
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system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.023887 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 3530 # number of overall hits
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system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 138 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use
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system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency
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system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses
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system.cpu.icache.demand_misses 280 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.074920 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 14941 # number of overall hits
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system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses
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system.cpu.icache.overall_misses 280 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use
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system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.005622 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 184.236128 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 2 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 416 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 83600 # number of cpu cycles simulated
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system.cpu.num_insts 15175 # Number of instructions executed
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system.cpu.num_refs 3684 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
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---------- End Simulation Statistics ----------
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