c1aecc05e6
This patch extensively modifies DSENT so that it can be accessed using Python. To access the Python interface, DSENT needs to compiled as a shared library. For this purpose a CMakeLists.txt file has been added. Some of the code that is not required is being removed.
557 lines
26 KiB
C++
557 lines
26 KiB
C++
/* Copyright (c) 2012 Massachusetts Institute of Technology
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "model/electrical/router/Router.h"
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#include <cmath>
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#include <vector>
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#include "model/PortInfo.h"
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#include "model/EventInfo.h"
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#include "model/TransitionInfo.h"
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#include "model/ModelGen.h"
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#include "model/std_cells/StdCellLib.h"
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#include "model/std_cells/StdCell.h"
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#include "model/electrical/router/RouterInputPort.h"
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#include "model/electrical/router/RouterSwitchAllocator.h"
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#include "model/timing_graph/ElectricalNet.h"
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namespace DSENT
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{
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using std::sqrt;
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using std::vector;
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using LibUtil::castStringVector;
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using LibUtil::vectorToString;
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Router::Router(const String& instance_name_, const TechModel* tech_model_)
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: ElectricalModel(instance_name_, tech_model_)
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{
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initParameters();
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initProperties();
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}
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Router::~Router()
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{}
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void Router::initParameters()
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{
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addParameterName("NumberInputPorts");
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addParameterName("NumberOutputPorts");
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addParameterName("NumberBitsPerFlit");
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addParameterName("NumberVirtualNetworks");
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addParameterName("NumberVirtualChannelsPerVirtualNetwork");
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addParameterName("NumberBuffersPerVirtualChannel");
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// Spec for input port
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addParameterName("InputPort->BufferModel");
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// Spec for crossbar
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addParameterName("CrossbarModel");
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// Spec for switch allocator
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addParameterName("SwitchAllocator->ArbiterModel");
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// Spec for clock tree
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addParameterName("ClockTreeModel");
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addParameterName("ClockTree->NumberLevels");
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addParameterName("ClockTree->WireLayer");
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addParameterName("ClockTree->WireWidthMultiplier");
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addParameterName("ClockTree->WireSpacingMultiplier", 3.0);
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return;
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}
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void Router::initProperties()
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{
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return;
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}
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Router* Router::clone() const
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{
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// TODO
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return NULL;
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}
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void Router::constructModel()
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{
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// Get parameters
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unsigned int number_input_ports = getParameter("NumberInputPorts").toUInt();
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unsigned int number_output_ports = getParameter("NumberOutputPorts").toUInt();
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unsigned int number_bits_per_flit = getParameter("NumberBitsPerFlit").toUInt();
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ASSERT(number_input_ports > 0, "[Error] " + getInstanceName() +
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" -> Number of input ports must be > 0!");
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ASSERT(number_output_ports > 0, "[Error] " + getInstanceName() +
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" -> Number of output ports must be > 0!");
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ASSERT(number_bits_per_flit > 0, "[Error] " + getInstanceName() +
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" -> Number of bits per buffer must be > 0!");
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// Create ports
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createInputPort("CK");
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for(unsigned int i = 0; i < number_input_ports; ++i)
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{
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createInputPort("FlitIn" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
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}
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for(unsigned int i = 0; i < number_output_ports; ++i)
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{
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createOutputPort("FlitOut" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
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}
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// Create area, power, event results
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createElectricalResults();
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getEventInfo("Idle")->setStaticTransitionInfos();
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getEventInfo("Idle")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
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createElectricalEventResult("ReadBuffer");
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getEventInfo("ReadBuffer")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
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createElectricalEventResult("WriteBuffer");
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getEventInfo("WriteBuffer")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
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for(unsigned int i = 1; i <= number_output_ports; ++i)
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{
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createElectricalEventResult("TraverseCrossbar->Multicast" + (String)i);
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getEventInfo("TraverseCrossbar->Multicast" + (String)i)->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
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}
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createElectricalEventResult("ArbitrateSwitch->ArbitrateStage1");
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createElectricalEventResult("ArbitrateSwitch->ArbitrateStage2");
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createElectricalEventResult("DistributeClock");
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getEventInfo("DistributeClock")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0));
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// Create intermediate nets
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createNet("PipelineReg0_In");
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createNet("PipelineReg0_Out");
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createNet("PipelineReg1_In");
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createNet("PipelineReg1_Out");
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for(unsigned int i = 0; i < number_output_ports; ++i)
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{
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createNet("PipelineReg2_In" + (String)i);
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createNet("PipelineReg2_Out" + (String)i);
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}
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createRouterInputPort();
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createSwitchAllocator();
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createVirtualChannelAllocator();
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createCrossbar();
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createClockTree();
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createPipelineReg();
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// Get generated numbers
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unsigned int number_crossbar_selects = getGenProperties()->get("Crossbar->NumberSelects");
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// Add write buffer event
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getEventResult("WriteBuffer")->addSubResult(getSubInstance("PipelineReg0")->getEventResult("DFFD"), "PipelineReg0", number_bits_per_flit);
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getEventResult("WriteBuffer")->addSubResult(getSubInstance("PipelineReg0")->getEventResult("DFFQ"), "PipelineReg0", number_bits_per_flit);
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getEventResult("WriteBuffer")->addSubResult(getSubInstance("PipelineReg0")->getEventResult("CK"), "PipelineReg0", number_bits_per_flit);
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getEventResult("WriteBuffer")->addSubResult(getSubInstance("InputPort")->getEventResult("WriteBuffer"), "InputPort", 1.0);
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// Add read buffer event
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getEventResult("ReadBuffer")->addSubResult(getSubInstance("InputPort")->getEventResult("ReadBuffer"), "InputPort", 1.0);
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getEventResult("ReadBuffer")->addSubResult(getSubInstance("PipelineReg1")->getEventResult("DFFD"), "PipelineReg1", number_bits_per_flit);
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getEventResult("ReadBuffer")->addSubResult(getSubInstance("PipelineReg1")->getEventResult("DFFQ"), "PipelineReg1", number_bits_per_flit);
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getEventResult("ReadBuffer")->addSubResult(getSubInstance("PipelineReg1")->getEventResult("CK"), "PipelineReg1", number_bits_per_flit);
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// Add crossbar traversal event
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for(unsigned int i = 1; i <= number_output_ports; ++i)
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{
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Result* traverse_crossbar_event = getEventResult("TraverseCrossbar->Multicast" + (String)i);
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traverse_crossbar_event->addSubResult(getSubInstance("Crossbar_Sel_DFF")->getEventResult("DFFD"), "Crossbar_Sel_DFF", number_crossbar_selects);
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traverse_crossbar_event->addSubResult(getSubInstance("Crossbar_Sel_DFF")->getEventResult("DFFQ"), "Crossbar_Sel_DFF", number_crossbar_selects);
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traverse_crossbar_event->addSubResult(getSubInstance("Crossbar_Sel_DFF")->getEventResult("CK"), "Crossbar_Sel_DFF", number_crossbar_selects);
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traverse_crossbar_event->addSubResult(getSubInstance("Crossbar")->getEventResult("Multicast" + (String)i), "Crossbar", 1.0);
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for(unsigned int j = 0; j < i; ++j)
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{
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traverse_crossbar_event->addSubResult(getSubInstance("PipelineReg2_" + (String)j)->getEventResult("DFFD"), "PipelineReg2_" + (String)j, number_bits_per_flit);
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traverse_crossbar_event->addSubResult(getSubInstance("PipelineReg2_" + (String)j)->getEventResult("DFFQ"), "PipelineReg2_" + (String)j, number_bits_per_flit);
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traverse_crossbar_event->addSubResult(getSubInstance("PipelineReg2_" + (String)j)->getEventResult("CK"), "PipelineReg2_" + (String)j, number_bits_per_flit);
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}
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}
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// Add stage1 allocator arbitrate
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Result* arb_sw_stage1_event = getEventResult("ArbitrateSwitch->ArbitrateStage1");
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arb_sw_stage1_event->addSubResult(getSubInstance("SwitchAllocator")->getEventResult("ArbitrateStage1"), "SwitchAllocator", 1.0);
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// Add stage2 allocator arbitrate
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Result* arb_sw_stage2_event = getEventResult("ArbitrateSwitch->ArbitrateStage2");
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arb_sw_stage2_event->addSubResult(getSubInstance("SwitchAllocator")->getEventResult("ArbitrateStage2"), "SwitchAllocator", 1.0);
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// Add CK event
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getEventResult("DistributeClock")->addSubResult(getSubInstance("ClockTree")->getEventResult("Send"), "ClockTree", 1.0);
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return;
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}
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void Router::updateModel()
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{
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// Get parameters
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unsigned int number_output_ports = getParameter("NumberOutputPorts").toUInt();
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// Update other components
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getSubInstance("PipelineReg0")->update();
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getSubInstance("InputPort")->update();
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getSubInstance("PipelineReg1")->update();
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getSubInstance("Crossbar_Sel_DFF")->update();
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getSubInstance("Crossbar")->update();
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for(unsigned int i = 0; i < number_output_ports; ++i)
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{
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getSubInstance("PipelineReg2_" + (String)i)->update();
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}
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getSubInstance("SwitchAllocator")->update();
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// Update clock tree
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double total_clock_tree_cap = getNet("CK")->getTotalDownstreamCap();
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double router_area = getAreaResult("Active")->calculateSum();
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Model* clock_tree = getSubInstance("ClockTree");
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clock_tree->setProperty("SitePitch", sqrt(router_area));
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clock_tree->setProperty("TotalLoadCapPerBit", total_clock_tree_cap);
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clock_tree->update();
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return;
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}
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void Router::propagateTransitionInfo()
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{
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// Update probability
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unsigned int number_output_ports = getParameter("NumberOutputPorts");
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// Current event
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const String& current_event = getGenProperties()->get("UseModelEvent");
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ElectricalModel* pipeline_reg0 = (ElectricalModel*)getSubInstance("PipelineReg0");
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propagatePortTransitionInfo(pipeline_reg0, "D", "FlitIn0");
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propagatePortTransitionInfo(pipeline_reg0, "CK", "CK");
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pipeline_reg0->use();
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ElectricalModel* input_port = (ElectricalModel*)getSubInstance("InputPort");
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propagatePortTransitionInfo(input_port, "FlitIn", pipeline_reg0, "Q");
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propagatePortTransitionInfo(input_port, "CK", "CK");
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input_port->getGenProperties()->set("UseModelEvent", "ReadWrite");
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input_port->use();
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ElectricalModel* pipeline_reg1 = (ElectricalModel*)getSubInstance("PipelineReg1");
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propagatePortTransitionInfo(pipeline_reg1, "D", "FlitIn0");
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propagatePortTransitionInfo(pipeline_reg1, "CK", "CK");
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pipeline_reg1->use();
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ElectricalModel* crossbar_sel_dff = (ElectricalModel*)getSubInstance("Crossbar_Sel_DFF");
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assignPortTransitionInfo(crossbar_sel_dff, "D", TransitionInfo());
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propagatePortTransitionInfo(crossbar_sel_dff, "CK", "CK");
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crossbar_sel_dff->use();
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ElectricalModel* crossbar = (ElectricalModel*)getSubInstance("Crossbar");
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bool is_crossbar_event = false;
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for(unsigned int i = 1; i <= number_output_ports; ++i)
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{
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if(current_event == ("TraverseCrossbar->Multicast" + (String)i))
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{
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is_crossbar_event = true;
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// Assume the flit is sent from port 0 to port 0~i-1
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// Apply default transition info
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crossbar->applyTransitionInfo("Multicast" + (String)i);
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// Overwrite transition info
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propagatePortTransitionInfo(crossbar, "In0", "FlitIn0");
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break;
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}
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}
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if(is_crossbar_event == false)
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{
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crossbar->applyTransitionInfo("Multicast1");
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propagatePortTransitionInfo(crossbar, "In0", "FlitIn0");
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}
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crossbar->use();
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vector<ElectricalModel*> pipeline_reg2s(number_output_ports, NULL);
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for(unsigned int i = 0; i < number_output_ports; ++i)
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{
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pipeline_reg2s[i] = (ElectricalModel*)getSubInstance("PipelineReg2_" + (String)i);
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propagatePortTransitionInfo(pipeline_reg2s[i], "D", "FlitIn0");
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propagatePortTransitionInfo(pipeline_reg2s[i], "CK", "CK");
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pipeline_reg2s[i]->use();
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}
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ElectricalModel* sw_allocator = (ElectricalModel*)getSubInstance("SwitchAllocator");
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if(current_event == "ArbitrateSwitch->ArbitrateStage1")
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{
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sw_allocator->applyTransitionInfo("ArbitrateStage1");
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}
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else if(current_event == "ArbitrateSwitch->ArbitrateStage2")
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{
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sw_allocator->applyTransitionInfo("ArbitrateStage2");
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}
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else
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{
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sw_allocator->applyTransitionInfo("Idle");
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}
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sw_allocator->use();
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ElectricalModel* clock_tree = (ElectricalModel*)getSubInstance("ClockTree");
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propagatePortTransitionInfo(clock_tree, "In", "CK");
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clock_tree->use();
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return;
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}
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void Router::createRouterInputPort()
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{
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// Get parameters
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unsigned int number_input_ports = getParameter("NumberInputPorts").toUInt();
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unsigned int number_vns = getParameter("NumberVirtualNetworks").toUInt();
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const String& number_vcs_per_vn = getParameter("NumberVirtualChannelsPerVirtualNetwork");
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const String& number_bufs_per_vc = getParameter("NumberBuffersPerVirtualChannel");
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unsigned int number_bits_per_flit = getParameter("NumberBitsPerFlit").toUInt();
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const String& buffer_model = getParameter("InputPort->BufferModel");
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// Init input port model
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const String& input_port_name = "InputPort";
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RouterInputPort* input_port = new RouterInputPort(input_port_name, getTechModel());
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input_port->setParameter("NumberVirtualNetworks", number_vns);
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input_port->setParameter("NumberVirtualChannelsPerVirtualNetwork", number_vcs_per_vn);
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input_port->setParameter("NumberBuffersPerVirtualChannel", number_bufs_per_vc);
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input_port->setParameter("NumberBitsPerFlit", number_bits_per_flit);
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input_port->setParameter("BufferModel", buffer_model);
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input_port->construct();
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unsigned int number_input_port_outputs = input_port->getGenProperties()->get("NumberOutputs");
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unsigned int number_input_port_addr_bits = input_port->getGenProperties()->get("NumberAddressBits");
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getGenProperties()->set("InputPort->NumberOutputs", number_input_port_outputs);
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getGenProperties()->set("InputPort->NumberAddressBits", number_input_port_addr_bits);
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unsigned int total_number_vcs = input_port->getGenProperties()->get("TotalNumberVirtualChannels");
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getGenProperties()->set("TotalNumberVirtualChannels", total_number_vcs);
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// Add the instance and the results
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addSubInstances(input_port, number_input_ports);
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addElectricalSubResults(input_port, number_input_ports);
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// Create connections
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createNet("InputPort_In", makeNetIndex(0, number_bits_per_flit-1));
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createNet("InputPort_Out", makeNetIndex(0, number_bits_per_flit-1));
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assignVirtualFanout("InputPort_In", "PipelineReg0_Out");
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portConnect(input_port, "FlitIn", "InputPort_In");
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portConnect(input_port, "CK", "CK");
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portConnect(input_port, "FlitOut", "InputPort_Out");
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assignVirtualFanin("PipelineReg1_In", "InputPort_Out");
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return;
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}
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void Router::createVirtualChannelAllocator()
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{}
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void Router::createSwitchAllocator()
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{
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// Get parameters
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unsigned int number_input_ports = getParameter("NumberInputPorts").toUInt();
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unsigned int number_output_ports = getParameter("NumberOutputPorts").toUInt();
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unsigned int total_number_vcs = getGenProperties()->get("TotalNumberVirtualChannels").toUInt();
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const String& arb_model = getParameter("SwitchAllocator->ArbiterModel");
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// Init switch allocator model
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const String& sw_allocator_name = "SwitchAllocator";
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RouterSwitchAllocator* sw_allocator = new RouterSwitchAllocator(sw_allocator_name, getTechModel());
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sw_allocator->setParameter("NumberInputPorts", number_input_ports);
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sw_allocator->setParameter("NumberOutputPorts", number_output_ports);
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sw_allocator->setParameter("TotalNumberVirtualChannels", total_number_vcs);
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sw_allocator->setParameter("ArbiterModel", arb_model);
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sw_allocator->construct();
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// Add the instance and the results
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addSubInstances(sw_allocator, 1.0);
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addElectricalSubResults(sw_allocator, 1.0);
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// Create connections (currently connect CK only)
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portConnect(sw_allocator, "CK", "CK");
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return;
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}
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void Router::createCrossbar()
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{
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// Get parameters
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const String& crossbar_model = getParameter("CrossbarModel");
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unsigned int number_input_ports = getParameter("NumberInputPorts").toUInt();
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unsigned int number_output_ports = getParameter("NumberOutputPorts").toUInt();
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unsigned int number_bits_per_flit = getParameter("NumberBitsPerFlit").toUInt();
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unsigned int number_input_port_outputs = getGenProperties()->get("InputPort->NumberOutputs").toUInt();
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unsigned int number_crossbar_inputs = number_input_port_outputs * number_input_ports;
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unsigned int number_crossbar_outputs = number_output_ports;
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getGenProperties()->set("Crossbar->NumberInputs", number_crossbar_inputs);
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getGenProperties()->set("Crossbar->NumberOutputs", number_crossbar_outputs);
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// Init crossbar model
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const String& crossbar_name = "Crossbar";
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ElectricalModel* crossbar = ModelGen::createCrossbar(crossbar_model, crossbar_name, getTechModel());
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crossbar->setParameter("NumberInputs", number_crossbar_inputs);
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crossbar->setParameter("NumberOutputs", number_crossbar_outputs);
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crossbar->setParameter("NumberBits", number_bits_per_flit);
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crossbar->setParameter("BitDuplicate", "TRUE");
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crossbar->construct();
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unsigned int number_crossbar_selects = crossbar->getGenProperties()->get("NumberSelectsPerPort");
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getGenProperties()->set("Crossbar->NumberSelects", number_crossbar_selects);
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// Init DFF for crossbar selections
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const String& crossbar_sel_dff_name = "Crossbar_Sel_DFF";
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StdCell* crossbar_sel_dff = getTechModel()->getStdCellLib()->createStdCell("DFFQ", crossbar_sel_dff_name);
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crossbar_sel_dff->construct();
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// Add instances and results
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addSubInstances(crossbar, 1.0);
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addElectricalSubResults(crossbar, 1.0);
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addSubInstances(crossbar_sel_dff, number_crossbar_outputs * number_crossbar_selects);
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addElectricalSubResults(crossbar_sel_dff, number_crossbar_outputs * number_crossbar_selects);
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// Create connections
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createNet("Crossbar_Sel_DFF_Out");
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for(unsigned int i = 0; i < number_crossbar_outputs; ++i)
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{
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for(unsigned int j = 0; j < number_crossbar_selects; ++j)
|
|
{
|
|
createNet(String::format("Crossbar_Sel%d_%d", i, j));
|
|
}
|
|
createNet("Crossbar_Out" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
|
|
}
|
|
for(unsigned int i = 0; i < number_crossbar_inputs; ++i)
|
|
{
|
|
createNet("Crossbar_In" + (String)i, makeNetIndex(0, number_bits_per_flit-1));
|
|
}
|
|
|
|
for(unsigned int i = 0; i < number_crossbar_selects; ++i)
|
|
{
|
|
portConnect(crossbar_sel_dff, "CK", "CK");
|
|
}
|
|
portConnect(crossbar_sel_dff, "Q", "Crossbar_Sel_DFF_Out");
|
|
for(unsigned int i = 0; i < number_crossbar_inputs; ++i)
|
|
{
|
|
assignVirtualFanout("Crossbar_In" + (String)i, "PipelineReg1_Out");
|
|
portConnect(crossbar, "In" + (String)i, "Crossbar_In" + (String)i);
|
|
}
|
|
for(unsigned int i = 0; i < number_crossbar_outputs; ++i)
|
|
{
|
|
for(unsigned int j = 0; j < number_crossbar_selects; ++j)
|
|
{
|
|
assignVirtualFanout(String::format("Crossbar_Sel%d_%d", i, j), "Crossbar_Sel_DFF_Out");
|
|
portConnect(crossbar, String::format("Sel%d_%d", i, j), String::format("Crossbar_Sel%d_%d", i, j));
|
|
}
|
|
portConnect(crossbar, "Out" + (String)i, "Crossbar_Out" + (String)i);
|
|
assignVirtualFanin("PipelineReg2_In" + (String)i, "Crossbar_Out" + (String)i);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
void Router::createPipelineReg()
|
|
{
|
|
// Get parameters
|
|
unsigned int number_input_ports = getParameter("NumberInputPorts").toUInt();
|
|
unsigned int number_output_ports = getParameter("NumberOutputPorts").toUInt();
|
|
unsigned int number_bits_per_flit = getParameter("NumberBitsPerFlit").toUInt();
|
|
unsigned int number_crossbar_inputs = getGenProperties()->get("Crossbar->NumberInputs");
|
|
|
|
// Init pipeline reg model
|
|
// First stage: from router input to input port
|
|
const String& pipeline_reg0_name = "PipelineReg0";
|
|
StdCell* pipeline_reg0 = getTechModel()->getStdCellLib()->createStdCell("DFFQ", pipeline_reg0_name);
|
|
pipeline_reg0->construct();
|
|
// Second stage: from input port to crossbar
|
|
const String& pipeline_reg1_name = "PipelineReg1";
|
|
StdCell* pipeline_reg1 = getTechModel()->getStdCellLib()->createStdCell("DFFQ", pipeline_reg1_name);
|
|
pipeline_reg1->construct();
|
|
|
|
// Third stage: from crossbar to router output
|
|
vector<StdCell*> pipeline_reg2s(number_output_ports, (StdCell*)NULL);
|
|
vector<String> pipeline_reg2_names(number_output_ports, "");
|
|
for(unsigned int i = 0; i < number_output_ports; ++i)
|
|
{
|
|
pipeline_reg2_names[i] = "PipelineReg2_" + (String)i;
|
|
pipeline_reg2s[i] = getTechModel()->getStdCellLib()->createStdCell("DFFQ", pipeline_reg2_names[i]);
|
|
pipeline_reg2s[i]->construct();
|
|
}
|
|
|
|
// Add instances and results
|
|
addSubInstances(pipeline_reg0, number_input_ports * number_bits_per_flit);
|
|
addElectricalSubResults(pipeline_reg0, number_input_ports * number_bits_per_flit);
|
|
|
|
addSubInstances(pipeline_reg1, number_crossbar_inputs * number_bits_per_flit);
|
|
addElectricalSubResults(pipeline_reg1, number_crossbar_inputs * number_bits_per_flit);
|
|
|
|
for(unsigned int i = 0; i < number_output_ports; ++i)
|
|
{
|
|
addSubInstances(pipeline_reg2s[i], number_bits_per_flit);
|
|
addElectricalSubResults(pipeline_reg2s[i], number_bits_per_flit);
|
|
}
|
|
|
|
// Create data connections
|
|
for(unsigned int i = 0; i < number_input_ports; ++i)
|
|
{
|
|
assignVirtualFanin("PipelineReg0_In", "FlitIn" + (String)i);
|
|
}
|
|
portConnect(pipeline_reg0, "D", "PipelineReg0_In");
|
|
portConnect(pipeline_reg0, "Q", "PipelineReg0_Out");
|
|
portConnect(pipeline_reg1, "D", "PipelineReg1_In");
|
|
portConnect(pipeline_reg1, "Q", "PipelineReg1_Out");
|
|
for(unsigned int i = 0; i < number_output_ports; ++i)
|
|
{
|
|
portConnect(pipeline_reg2s[i], "D", "PipelineReg2_In" + (String)i);
|
|
portConnect(pipeline_reg2s[i], "Q", "PipelineReg2_Out" + (String)i);
|
|
assignVirtualFanout("FlitOut" + (String)i, "PipelineReg2_Out" + (String)i);
|
|
}
|
|
|
|
// Create CK connections
|
|
for(unsigned int n = 0; n < number_bits_per_flit; ++n)
|
|
{
|
|
for(unsigned int i = 0; i < number_input_ports; ++i)
|
|
{
|
|
portConnect(pipeline_reg0, "CK", "CK");
|
|
}
|
|
for(unsigned int i = 0; i < number_crossbar_inputs; ++i)
|
|
{
|
|
portConnect(pipeline_reg1, "CK", "CK");
|
|
}
|
|
for(unsigned int i = 0; i < number_output_ports; ++i)
|
|
{
|
|
portConnect(pipeline_reg2s[i], "CK", "CK");
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
void Router::createClockTree()
|
|
{
|
|
// Get parameters
|
|
const String& clock_tree_model = getParameter("ClockTreeModel");
|
|
const String& clock_tree_number_levels = getParameter("ClockTree->NumberLevels");
|
|
const String& clock_tree_wire_layer = getParameter("ClockTree->WireLayer");
|
|
const String& clock_tree_wire_width_multiplier = getParameter("ClockTree->WireWidthMultiplier");
|
|
const String& clock_tree_wire_spacing_multiplier = getParameter("ClockTree->WireSpacingMultiplier");
|
|
|
|
// Init clock tree model
|
|
const String& clock_tree_name = "ClockTree";
|
|
ElectricalModel* clock_tree = (ElectricalModel*)ModelGen::createModel(clock_tree_model, clock_tree_name, getTechModel());
|
|
clock_tree->setParameter("NumberLevels", clock_tree_number_levels);
|
|
clock_tree->setParameter("NumberBits", 1);
|
|
clock_tree->setParameter("WireLayer", clock_tree_wire_layer);
|
|
clock_tree->setParameter("WireWidthMultiplier", clock_tree_wire_width_multiplier);
|
|
clock_tree->setParameter("WireSpacingMultiplier", clock_tree_wire_spacing_multiplier);
|
|
clock_tree->construct();
|
|
|
|
// Add instances and results
|
|
addSubInstances(clock_tree, 1.0);
|
|
addElectricalSubResults(clock_tree, 1.0);
|
|
|
|
return;
|
|
}
|
|
} // namespace DSENT
|
|
|