89cf3f6e85
These files really aren't general enough to belong in src/base. This patch doesn't reorder include lines, leaving them unsorted in many cases, but Nate's magic script will fix that up shortly. --HG-- rename : src/base/sched_list.hh => src/cpu/sched_list.hh rename : src/base/timebuf.hh => src/cpu/timebuf.hh
553 lines
18 KiB
C++
553 lines
18 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_IEW_HH__
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#define __CPU_O3_IEW_HH__
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#include <queue>
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#include "base/statistics.hh"
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#include "cpu/timebuf.hh"
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#include "config/full_system.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/o3/scoreboard.hh"
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#include "cpu/o3/lsq.hh"
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class DerivO3CPUParams;
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class FUPool;
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/**
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* DefaultIEW handles both single threaded and SMT IEW
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* (issue/execute/writeback). It handles the dispatching of
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* instructions to the LSQ/IQ as part of the issue stage, and has the
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* IQ try to issue instructions each cycle. The execute latency is
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* actually tied into the issue latency to allow the IQ to be able to
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* do back-to-back scheduling without having to speculatively schedule
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* instructions. This happens by having the IQ have access to the
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* functional units, and the IQ gets the execution latencies from the
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* FUs when it issues instructions. Instructions reach the execute
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* stage on the last cycle of their execution, which is when the IQ
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* knows to wake up any dependent instructions, allowing back to back
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* scheduling. The execute portion of IEW separates memory
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* instructions from non-memory instructions, either telling the LSQ
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* to execute the instruction, or executing the instruction directly.
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* The writeback portion of IEW completes the instructions by waking
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* up any dependents, and marking the register ready on the
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* scoreboard.
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*/
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template<class Impl>
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class DefaultIEW
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{
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private:
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//Typedefs from Impl
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::O3CPU O3CPU;
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typedef typename CPUPol::IQ IQ;
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typedef typename CPUPol::RenameMap RenameMap;
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typedef typename CPUPol::LSQ LSQ;
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typedef typename CPUPol::TimeStruct TimeStruct;
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typedef typename CPUPol::IEWStruct IEWStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::IssueStruct IssueStruct;
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friend class Impl::O3CPU;
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friend class CPUPol::IQ;
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public:
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/** Overall IEW stage status. Used to determine if the CPU can
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* deschedule itself due to a lack of activity.
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*/
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enum Status {
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Active,
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Inactive
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};
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/** Status for Issue, Execute, and Writeback stages. */
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enum StageStatus {
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Running,
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Blocked,
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Idle,
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StartSquash,
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Squashing,
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Unblocking
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};
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private:
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/** Overall stage status. */
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Status _status;
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/** Dispatch status. */
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StageStatus dispatchStatus[Impl::MaxThreads];
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/** Execute status. */
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StageStatus exeStatus;
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/** Writeback status. */
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StageStatus wbStatus;
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public:
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/** Constructs a DefaultIEW with the given parameters. */
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DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
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/** Returns the name of the DefaultIEW stage. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Initializes stage; sends back the number of free IQ and LSQ entries. */
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void initStage();
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/** Returns the dcache port. */
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Port *getDcachePort() { return ldstQueue.getDcachePort(); }
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/** Sets main time buffer used for backwards communication. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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/** Sets time buffer for getting instructions coming from rename. */
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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/** Sets time buffer to pass on instructions to commit. */
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void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Sets pointer to the scoreboard. */
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void setScoreboard(Scoreboard *sb_ptr);
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/** Drains IEW stage. */
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bool drain();
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/** Resumes execution after a drain. */
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void resume();
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/** Completes switch out of IEW stage. */
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void switchOut();
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Returns if IEW is switched out. */
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bool isSwitchedOut() { return switchedOut; }
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/** Squashes instructions in IEW for a specific thread. */
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void squash(ThreadID tid);
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/** Wakes all dependents of a completed instruction. */
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void wakeDependents(DynInstPtr &inst);
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/** Tells memory dependence unit that a memory instruction needs to be
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* rescheduled. It will re-execute once replayMemInst() is called.
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*/
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void rescheduleMemInst(DynInstPtr &inst);
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/** Re-executes all rescheduled memory instructions. */
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void replayMemInst(DynInstPtr &inst);
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/** Sends an instruction to commit through the time buffer. */
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void instToCommit(DynInstPtr &inst);
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/** Inserts unused instructions of a thread into the skid buffer. */
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void skidInsert(ThreadID tid);
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/** Returns the max of the number of entries in all of the skid buffers. */
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int skidCount();
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/** Returns if all of the skid buffers are empty. */
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bool skidsEmpty();
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/** Updates overall IEW status based on all of the stages' statuses. */
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void updateStatus();
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/** Resets entries of the IQ and the LSQ. */
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void resetEntries();
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/** Tells the CPU to wakeup if it has descheduled itself due to no
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* activity. Used mainly by the LdWritebackEvent.
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*/
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void wakeCPU();
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/** Reports to the CPU that there is activity this cycle. */
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void activityThisCycle();
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/** Tells CPU that the IEW stage is active and running. */
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inline void activateStage();
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/** Tells CPU that the IEW stage is inactive and idle. */
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inline void deactivateStage();
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/** Returns if the LSQ has any stores to writeback. */
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bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
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/** Returns if the LSQ has any stores to writeback. */
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bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
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void incrWb(InstSeqNum &sn)
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{
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if (++wbOutstanding == wbMax)
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ableToIssue = false;
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DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
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assert(wbOutstanding <= wbMax);
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#ifdef DEBUG
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wbList.insert(sn);
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#endif
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}
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void decrWb(InstSeqNum &sn)
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{
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if (wbOutstanding-- == wbMax)
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ableToIssue = true;
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DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
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assert(wbOutstanding >= 0);
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#ifdef DEBUG
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assert(wbList.find(sn) != wbList.end());
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wbList.erase(sn);
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#endif
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}
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#ifdef DEBUG
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std::set<InstSeqNum> wbList;
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void dumpWb()
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{
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std::set<InstSeqNum>::iterator wb_it = wbList.begin();
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while (wb_it != wbList.end()) {
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cprintf("[sn:%lli]\n",
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(*wb_it));
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wb_it++;
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}
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}
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#endif
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bool canIssue() { return ableToIssue; }
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bool ableToIssue;
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/** Check misprediction */
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void checkMisprediction(DynInstPtr &inst);
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private:
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/** Sends commit proper information for a squash due to a branch
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* mispredict.
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*/
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void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
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/** Sends commit proper information for a squash due to a memory order
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* violation.
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*/
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void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
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/** Sends commit proper information for a squash due to memory becoming
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* blocked (younger issued instructions must be retried).
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*/
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void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
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/** Sets Dispatch to blocked, and signals back to other stages to block. */
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void block(ThreadID tid);
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/** Unblocks Dispatch if the skid buffer is empty, and signals back to
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* other stages to unblock.
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*/
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void unblock(ThreadID tid);
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/** Determines proper actions to take given Dispatch's status. */
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void dispatch(ThreadID tid);
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/** Dispatches instructions to IQ and LSQ. */
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void dispatchInsts(ThreadID tid);
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/** Executes instructions. In the case of memory operations, it informs the
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* LSQ to execute the instructions. Also handles any redirects that occur
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* due to the executed instructions.
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*/
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void executeInsts();
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/** Writebacks instructions. In our model, the instruction's execute()
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* function atomically reads registers, executes, and writes registers.
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* Thus this writeback only wakes up dependent instructions, and informs
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* the scoreboard of registers becoming ready.
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*/
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void writebackInsts();
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/** Returns the number of valid, non-squashed instructions coming from
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* rename to dispatch.
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*/
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unsigned validInstsFromRename();
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/** Reads the stall signals. */
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void readStallSignals(ThreadID tid);
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/** Checks if any of the stall conditions are currently true. */
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bool checkStall(ThreadID tid);
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/** Processes inputs and changes state accordingly. */
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void checkSignalsAndUpdate(ThreadID tid);
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/** Removes instructions from rename from a thread's instruction list. */
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void emptyRenameInsts(ThreadID tid);
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/** Sorts instructions coming from rename into lists separated by thread. */
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void sortInsts();
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public:
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/** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
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* Writeback to run for one cycle.
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*/
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void tick();
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private:
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/** Updates execution stats based on the instruction. */
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void updateExeInstStats(DynInstPtr &inst);
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/** Pointer to main time buffer used for backwards communication. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toFetch;
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/** Wire to get commit's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toRename;
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/** Rename instruction queue interface. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to get rename's output from rename queue. */
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typename TimeBuffer<RenameStruct>::wire fromRename;
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/** Issue stage queue. */
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TimeBuffer<IssueStruct> issueToExecQueue;
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/** Wire to read information from the issue stage time queue. */
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typename TimeBuffer<IssueStruct>::wire fromIssue;
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/**
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* IEW stage time buffer. Holds ROB indices of instructions that
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* can be marked as completed.
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*/
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TimeBuffer<IEWStruct> *iewQueue;
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/** Wire to write infromation heading to commit. */
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typename TimeBuffer<IEWStruct>::wire toCommit;
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/** Queue of all instructions coming from rename this cycle. */
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std::queue<DynInstPtr> insts[Impl::MaxThreads];
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/** Skid buffer between rename and IEW. */
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std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
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/** Scoreboard pointer. */
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Scoreboard* scoreboard;
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private:
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/** CPU pointer. */
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O3CPU *cpu;
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/** Records if IEW has written to the time buffer this cycle, so that the
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* CPU can deschedule itself if there is no activity.
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*/
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bool wroteToTimeBuffer;
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/** Source of possible stalls. */
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struct Stalls {
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bool commit;
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};
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/** Stages that are telling IEW to stall. */
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Stalls stalls[Impl::MaxThreads];
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/** Debug function to print instructions that are issued this cycle. */
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void printAvailableInsts();
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public:
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/** Instruction queue. */
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IQ instQueue;
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/** Load / store queue. */
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LSQ ldstQueue;
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/** Pointer to the functional unit pool. */
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FUPool *fuPool;
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/** Records if the LSQ needs to be updated on the next cycle, so that
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* IEW knows if there will be activity on the next cycle.
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*/
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bool updateLSQNextCycle;
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private:
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/** Records if there is a fetch redirect on this cycle for each thread. */
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bool fetchRedirect[Impl::MaxThreads];
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/** Records if the queues have been changed (inserted or issued insts),
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* so that IEW knows to broadcast the updated amount of free entries.
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*/
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bool updatedQueues;
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/** Commit to IEW delay, in ticks. */
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unsigned commitToIEWDelay;
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/** Rename to IEW delay, in ticks. */
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unsigned renameToIEWDelay;
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/**
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* Issue to execute delay, in ticks. What this actually represents is
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* the amount of time it takes for an instruction to wake up, be
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* scheduled, and sent to a FU for execution.
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*/
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unsigned issueToExecuteDelay;
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/** Width of dispatch, in instructions. */
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unsigned dispatchWidth;
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/** Width of issue, in instructions. */
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unsigned issueWidth;
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/** Index into queue of instructions being written back. */
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unsigned wbNumInst;
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/** Cycle number within the queue of instructions being written back.
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* Used in case there are too many instructions writing back at the current
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* cycle and writesbacks need to be scheduled for the future. See comments
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* in instToCommit().
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*/
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unsigned wbCycle;
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/** Number of instructions in flight that will writeback. */
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/** Number of instructions in flight that will writeback. */
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int wbOutstanding;
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/** Writeback width. */
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unsigned wbWidth;
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/** Writeback width * writeback depth, where writeback depth is
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* the number of cycles of writing back instructions that can be
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* buffered. */
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unsigned wbMax;
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/** Number of active threads. */
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ThreadID numThreads;
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/** Pointer to list of active threads. */
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std::list<ThreadID> *activeThreads;
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/** Maximum size of the skid buffer. */
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unsigned skidBufferMax;
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/** Is this stage switched out. */
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bool switchedOut;
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/** Stat for total number of idle cycles. */
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Stats::Scalar iewIdleCycles;
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/** Stat for total number of squashing cycles. */
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Stats::Scalar iewSquashCycles;
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/** Stat for total number of blocking cycles. */
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Stats::Scalar iewBlockCycles;
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/** Stat for total number of unblocking cycles. */
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Stats::Scalar iewUnblockCycles;
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/** Stat for total number of instructions dispatched. */
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Stats::Scalar iewDispatchedInsts;
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/** Stat for total number of squashed instructions dispatch skips. */
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Stats::Scalar iewDispSquashedInsts;
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/** Stat for total number of dispatched load instructions. */
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Stats::Scalar iewDispLoadInsts;
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/** Stat for total number of dispatched store instructions. */
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Stats::Scalar iewDispStoreInsts;
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/** Stat for total number of dispatched non speculative instructions. */
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Stats::Scalar iewDispNonSpecInsts;
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/** Stat for number of times the IQ becomes full. */
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Stats::Scalar iewIQFullEvents;
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/** Stat for number of times the LSQ becomes full. */
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Stats::Scalar iewLSQFullEvents;
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/** Stat for total number of memory ordering violation events. */
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Stats::Scalar memOrderViolationEvents;
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/** Stat for total number of incorrect predicted taken branches. */
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Stats::Scalar predictedTakenIncorrect;
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/** Stat for total number of incorrect predicted not taken branches. */
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Stats::Scalar predictedNotTakenIncorrect;
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/** Stat for total number of mispredicted branches detected at execute. */
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Stats::Formula branchMispredicts;
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/** Stat for total number of executed instructions. */
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Stats::Scalar iewExecutedInsts;
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/** Stat for total number of executed load instructions. */
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Stats::Vector iewExecLoadInsts;
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/** Stat for total number of executed store instructions. */
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// Stats::Scalar iewExecStoreInsts;
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/** Stat for total number of squashed instructions skipped at execute. */
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Stats::Scalar iewExecSquashedInsts;
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/** Number of executed software prefetches. */
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Stats::Vector iewExecutedSwp;
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/** Number of executed nops. */
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Stats::Vector iewExecutedNop;
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/** Number of executed meomory references. */
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Stats::Vector iewExecutedRefs;
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/** Number of executed branches. */
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Stats::Vector iewExecutedBranches;
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/** Number of executed store instructions. */
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Stats::Formula iewExecStoreInsts;
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/** Number of instructions executed per cycle. */
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Stats::Formula iewExecRate;
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/** Number of instructions sent to commit. */
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Stats::Vector iewInstsToCommit;
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/** Number of instructions that writeback. */
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Stats::Vector writebackCount;
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/** Number of instructions that wake consumers. */
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Stats::Vector producerInst;
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/** Number of instructions that wake up from producers. */
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Stats::Vector consumerInst;
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/** Number of instructions that were delayed in writing back due
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* to resource contention.
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*/
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Stats::Vector wbPenalized;
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/** Number of instructions per cycle written back. */
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Stats::Formula wbRate;
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/** Average number of woken instructions per writeback. */
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Stats::Formula wbFanout;
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/** Number of instructions per cycle delayed in writing back . */
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Stats::Formula wbPenalizedRate;
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};
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#endif // __CPU_O3_IEW_HH__
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