8e75b6e2a5
Protect other pieces of code so that sparc compiles SE again
src/arch/sparc/SConscript:
Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
protect legion code so it doesn't try to compile under se
--HG--
extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
72 lines
2.3 KiB
C++
72 lines
2.3 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
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#define __ARCH_SPARC_MMAPED_IPR_HH__
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/**
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* @file
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*
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* ISA-specific helper functions for memory mapped IPR accesses.
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*/
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "mem/packet.hh"
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#include "arch/sparc/tlb.hh"
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namespace SparcISA
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{
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inline Tick
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handleIprRead(ThreadContext *xc, Packet *pkt)
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{
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#if FULL_SYSTEM
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return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
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#else
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panic("Shouldn't have a memory mapped register in SE\n");
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#endif
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}
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inline Tick
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handleIprWrite(ThreadContext *xc, Packet *pkt)
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{
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#if FULL_SYSTEM
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return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
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#else
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panic("Shouldn't have a memory mapped register in SE\n");
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#endif
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}
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} // namespace SparcISA
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#endif
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