Ron Dreslinski 6592045cbc Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu ... src/mem/cache/base_cache.cc: If we still have outstanding requests, need to schedule event again src/mem/cache/miss/miss_queue.cc: Need to use block size so overlapping requests match in the MSHR's src/mem/cache/miss/mshr.cc: Actually save the address, otherwise we can't match MSHR's --HG-- extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8		2006-07-10 17:16:15 -04:00
..
cache	Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu	2006-07-10 17:16:15 -04:00
config	Backing in more changsets, getting closer to compile	2006-06-28 14:35:00 -04:00
bridge.cc	Move SimObject creation and Port connection loops	2006-06-13 23:19:28 -04:00
bridge.hh	Move SimObject creation and Port connection loops	2006-06-13 23:19:28 -04:00
bus.cc	Add default responder to bus	2006-07-06 14:41:01 -04:00
bus.hh	Add default responder to bus	2006-07-06 14:41:01 -04:00
mem_object.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
mem_object.hh	Move SimObject creation and Port connection loops	2006-06-13 23:19:28 -04:00
packet.cc	Backing in more changsets, getting closer to compile	2006-06-28 14:35:00 -04:00
packet.hh	Fix offset calculation. Now L2's work with timing&atomic.	2006-07-10 12:35:18 -04:00
page_table.cc	change the page table from map to hash_map and create small cache to to speed up lookups	2006-06-27 15:04:11 -04:00
page_table.hh	change the page table from map to hash_map and create small cache to to speed up lookups	2006-06-27 15:04:11 -04:00
physical.cc	Move SimObject creation and Port connection loops	2006-06-13 23:19:28 -04:00
physical.hh	Move SimObject creation and Port connection loops	2006-06-13 23:19:28 -04:00
port.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
port.hh	Allow ports to be created without a name.	2006-06-25 00:24:50 -04:00
port_impl.hh	add write/read functions that have endian conversions in them	2006-06-08 19:03:58 -04:00
request.hh	All files compile in the mem directory except cache_builder	2006-06-30 10:25:25 -04:00
translating_port.cc	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
translating_port.hh	Updated Authors from bk prs info	2006-05-31 19:26:56 -04:00
vport.cc	Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.	2006-06-06 17:32:21 -04:00
vport.hh	add write/read functions that have endian conversions in them	2006-06-08 19:03:58 -04:00