95a0b18431
Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
147 lines
5.3 KiB
Python
147 lines
5.3 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Tushar Krishna
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../common')
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addToPath('../ruby')
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addToPath('../topologies')
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import Options
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import Ruby
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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parser.add_option("--synthetic", type="int", default=0,
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help="Synthetic Traffic type. 0 = Uniform Random,\
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1 = Tornado, 2 = Bit Complement")
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parser.add_option("-i", "--injectionrate", type="float", default=0.1,
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metavar="I",
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help="Injection rate in packets per cycle per node. \
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Takes decimal value between 0 to 1 (eg. 0.225). \
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Number of digits after 0 depends upon --precision.")
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parser.add_option("--precision", type="int", default=3,
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help="Number of digits of precision after decimal point\
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for injection rate")
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parser.add_option("--sim-cycles", type="int", default=1000,
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help="Number of simulation cycles")
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parser.add_option("--fixed-pkts", action="store_true",
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help="Network_test: inject --maxpackets and stop")
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parser.add_option("--maxpackets", type="int", default=1,
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help="Stop injecting after --maxpackets. \
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Works only with --fixed-pkts")
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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block_size = 64
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if options.num_cpus > block_size:
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print "Error: Number of cores %d limited to %d because of false sharing" \
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% (options.num_cpus, block_size)
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sys.exit(1)
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cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
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max_packets=options.maxpackets,
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sim_cycles=options.sim_cycles,
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traffic_type=options.synthetic,
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inj_rate=options.injectionrate,
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precision=options.precision,
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num_memories=options.num_dirs) \
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for i in xrange(options.num_cpus) ]
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# create the desired simulated system
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system = System(cpu = cpus, physmem = SimpleMemory(),
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mem_ranges = [AddrRange(options.mem_size)])
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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Ruby.create_system(options, False, system)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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i = 0
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for ruby_port in system.ruby._cpu_ports:
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#
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# Tie the cpu test ports to the ruby cpu port
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#
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cpus[i].test = ruby_port.slave
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i += 1
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(options.abs_max_tick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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