e21878c3f2
src/cpu/o3/iew_impl.hh:
Allow for slightly more flexible handling of non-speculative instructions. They can be other classes now, such as loads or stores.
Also be sure to clear the state associated with squashes that are not used. i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation.
Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load.
src/cpu/o3/inst_queue_impl.hh:
Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction. This prevents non-speculative instructions from being issued too early.
src/cpu/o3/mem_dep_unit_impl.hh:
Clear instruction's ability to issue if it's replayed.
--HG--
extra : convert_revision : d69dae878a30821222885485f4dee87170d56eb3
583 lines
17 KiB
C++
583 lines
17 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include <map>
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#include "cpu/o3/inst_queue.hh"
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#include "cpu/o3/mem_dep_unit.hh"
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template <class MemDepPred, class Impl>
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MemDepUnit<MemDepPred, Impl>::MemDepUnit()
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: loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
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storeBarrierSN(0), iqPtr(NULL)
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{
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}
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template <class MemDepPred, class Impl>
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MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
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: depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
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loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
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{
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DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
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}
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template <class MemDepPred, class Impl>
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MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
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{
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for (int tid=0; tid < Impl::MaxThreads; tid++) {
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ListIt inst_list_it = instList[tid].begin();
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MemDepHashIt hash_it;
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while (!instList[tid].empty()) {
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hash_it = memDepHash.find((*inst_list_it)->seqNum);
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assert(hash_it != memDepHash.end());
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memDepHash.erase(hash_it);
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instList[tid].erase(inst_list_it++);
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}
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}
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#ifdef DEBUG
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assert(MemDepEntry::memdep_count == 0);
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#endif
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}
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template <class MemDepPred, class Impl>
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std::string
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MemDepUnit<MemDepPred, Impl>::name() const
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{
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return "memdepunit";
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
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{
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DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
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id = tid;
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depPred.init(params->SSITSize, params->LFSTSize);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::regStats()
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{
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insertedLoads
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.name(name() + ".memDep.insertedLoads")
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.desc("Number of loads inserted to the mem dependence unit.");
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insertedStores
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.name(name() + ".memDep.insertedStores")
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.desc("Number of stores inserted to the mem dependence unit.");
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conflictingLoads
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.name(name() + ".memDep.conflictingLoads")
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.desc("Number of conflicting loads.");
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conflictingStores
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.name(name() + ".memDep.conflictingStores")
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.desc("Number of conflicting stores.");
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::switchOut()
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{
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assert(instList[0].empty());
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assert(instsToReplay.empty());
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assert(memDepHash.empty());
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// Clear any state.
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for (int i = 0; i < Impl::MaxThreads; ++i) {
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instList[i].clear();
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}
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instsToReplay.clear();
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memDepHash.clear();
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::takeOverFrom()
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{
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// Be sure to reset all state.
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loadBarrier = storeBarrier = false;
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loadBarrierSN = storeBarrierSN = 0;
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depPred.clear();
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
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{
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iqPtr = iq_ptr;
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
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{
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unsigned tid = inst->threadNumber;
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MemDepEntryPtr inst_entry = new MemDepEntry(inst);
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// Add the MemDepEntry to the hash.
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memDepHash.insert(
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std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
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#ifdef DEBUG
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MemDepEntry::memdep_insert++;
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#endif
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instList[tid].push_back(inst);
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inst_entry->listIt = --(instList[tid].end());
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// Check any barriers and the dependence predictor for any
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// producing memrefs/stores.
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InstSeqNum producing_store;
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if (inst->isLoad() && loadBarrier) {
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DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
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loadBarrierSN);
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producing_store = loadBarrierSN;
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} else if (inst->isStore() && storeBarrier) {
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DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
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storeBarrierSN);
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producing_store = storeBarrierSN;
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} else {
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producing_store = depPred.checkInst(inst->readPC());
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}
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MemDepEntryPtr store_entry = NULL;
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// If there is a producing store, try to find the entry.
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if (producing_store != 0) {
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DPRINTF(MemDepUnit, "Searching for producer\n");
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MemDepHashIt hash_it = memDepHash.find(producing_store);
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if (hash_it != memDepHash.end()) {
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store_entry = (*hash_it).second;
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DPRINTF(MemDepUnit, "Proucer found\n");
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}
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}
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// If no store entry, then instruction can issue as soon as the registers
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// are ready.
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if (!store_entry) {
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DPRINTF(MemDepUnit, "No dependency for inst PC "
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"%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
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inst_entry->memDepReady = true;
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if (inst->readyToIssue()) {
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inst_entry->regsReady = true;
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moveToReady(inst_entry);
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}
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} else {
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// Otherwise make the instruction dependent on the store/barrier.
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DPRINTF(MemDepUnit, "Adding to dependency list; "
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"inst PC %#x is dependent on [sn:%lli].\n",
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inst->readPC(), producing_store);
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if (inst->readyToIssue()) {
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inst_entry->regsReady = true;
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}
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// Clear the bit saying this instruction can issue.
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inst->clearCanIssue();
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// Add this instruction to the list of dependents.
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store_entry->dependInsts.push_back(inst_entry);
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if (inst->isLoad()) {
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++conflictingLoads;
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} else {
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++conflictingStores;
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}
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}
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if (inst->isStore()) {
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DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
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inst->readPC(), inst->seqNum);
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depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
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++insertedStores;
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} else if (inst->isLoad()) {
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++insertedLoads;
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} else {
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panic("Unknown type! (most likely a barrier).");
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
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{
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unsigned tid = inst->threadNumber;
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MemDepEntryPtr inst_entry = new MemDepEntry(inst);
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// Insert the MemDepEntry into the hash.
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memDepHash.insert(
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std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
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#ifdef DEBUG
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MemDepEntry::memdep_insert++;
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#endif
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// Add the instruction to the list.
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instList[tid].push_back(inst);
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inst_entry->listIt = --(instList[tid].end());
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// Might want to turn this part into an inline function or something.
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// It's shared between both insert functions.
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if (inst->isStore()) {
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DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
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inst->readPC(), inst->seqNum);
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depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
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++insertedStores;
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} else if (inst->isLoad()) {
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++insertedLoads;
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} else {
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panic("Unknown type! (most likely a barrier).");
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
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{
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InstSeqNum barr_sn = barr_inst->seqNum;
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// Memory barriers block loads and stores, write barriers only stores.
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if (barr_inst->isMemBarrier()) {
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loadBarrier = true;
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loadBarrierSN = barr_sn;
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storeBarrier = true;
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storeBarrierSN = barr_sn;
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DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
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} else if (barr_inst->isWriteBarrier()) {
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storeBarrier = true;
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storeBarrierSN = barr_sn;
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DPRINTF(MemDepUnit, "Inserted a write barrier\n");
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}
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unsigned tid = barr_inst->threadNumber;
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MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
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// Add the MemDepEntry to the hash.
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memDepHash.insert(
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std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
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#ifdef DEBUG
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MemDepEntry::memdep_insert++;
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#endif
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// Add the instruction to the instruction list.
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instList[tid].push_back(barr_inst);
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inst_entry->listIt = --(instList[tid].end());
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Marking registers as ready for "
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"instruction PC %#x [sn:%lli].\n",
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inst->readPC(), inst->seqNum);
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MemDepEntryPtr inst_entry = findInHash(inst);
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inst_entry->regsReady = true;
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if (inst_entry->memDepReady) {
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DPRINTF(MemDepUnit, "Instruction has its memory "
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"dependencies resolved, adding it to the ready list.\n");
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moveToReady(inst_entry);
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} else {
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DPRINTF(MemDepUnit, "Instruction still waiting on "
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"memory dependency.\n");
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Marking non speculative "
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"instruction PC %#x as ready [sn:%lli].\n",
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inst->readPC(), inst->seqNum);
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MemDepEntryPtr inst_entry = findInHash(inst);
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moveToReady(inst_entry);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
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{
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instsToReplay.push_back(inst);
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
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{
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DynInstPtr temp_inst;
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// For now this replay function replays all waiting memory ops.
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while (!instsToReplay.empty()) {
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temp_inst = instsToReplay.front();
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MemDepEntryPtr inst_entry = findInHash(temp_inst);
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DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
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"[sn:%lli].\n",
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temp_inst->readPC(), temp_inst->seqNum);
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moveToReady(inst_entry);
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instsToReplay.pop_front();
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}
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
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"[sn:%lli].\n",
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inst->readPC(), inst->seqNum);
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unsigned tid = inst->threadNumber;
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// Remove the instruction from the hash and the list.
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MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
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assert(hash_it != memDepHash.end());
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instList[tid].erase((*hash_it).second->listIt);
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(*hash_it).second = NULL;
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memDepHash.erase(hash_it);
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#ifdef DEBUG
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MemDepEntry::memdep_erase++;
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#endif
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}
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
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{
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wakeDependents(inst);
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completed(inst);
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InstSeqNum barr_sn = inst->seqNum;
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if (inst->isMemBarrier()) {
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assert(loadBarrier && storeBarrier);
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if (loadBarrierSN == barr_sn)
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loadBarrier = false;
|
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if (storeBarrierSN == barr_sn)
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storeBarrier = false;
|
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} else if (inst->isWriteBarrier()) {
|
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assert(storeBarrier);
|
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if (storeBarrierSN == barr_sn)
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storeBarrier = false;
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}
|
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}
|
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
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{
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// Only stores and barriers have dependents.
|
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if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
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return;
|
|
}
|
|
|
|
MemDepEntryPtr inst_entry = findInHash(inst);
|
|
|
|
for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
|
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MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
|
|
|
|
if (!woken_inst->inst) {
|
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// Potentially removed mem dep entries could be on this list
|
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continue;
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|
}
|
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|
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DPRINTF(MemDepUnit, "Waking up a dependent inst, "
|
|
"[sn:%lli].\n",
|
|
woken_inst->inst->seqNum);
|
|
|
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if (woken_inst->regsReady && !woken_inst->squashed) {
|
|
moveToReady(woken_inst);
|
|
} else {
|
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woken_inst->memDepReady = true;
|
|
}
|
|
}
|
|
|
|
inst_entry->dependInsts.clear();
|
|
}
|
|
|
|
template <class MemDepPred, class Impl>
|
|
void
|
|
MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
|
|
unsigned tid)
|
|
{
|
|
if (!instsToReplay.empty()) {
|
|
ListIt replay_it = instsToReplay.begin();
|
|
while (replay_it != instsToReplay.end()) {
|
|
if ((*replay_it)->threadNumber == tid &&
|
|
(*replay_it)->seqNum > squashed_num) {
|
|
instsToReplay.erase(replay_it++);
|
|
} else {
|
|
++replay_it;
|
|
}
|
|
}
|
|
}
|
|
|
|
ListIt squash_it = instList[tid].end();
|
|
--squash_it;
|
|
|
|
MemDepHashIt hash_it;
|
|
|
|
while (!instList[tid].empty() &&
|
|
(*squash_it)->seqNum > squashed_num) {
|
|
|
|
DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
|
|
(*squash_it)->seqNum);
|
|
|
|
hash_it = memDepHash.find((*squash_it)->seqNum);
|
|
|
|
assert(hash_it != memDepHash.end());
|
|
|
|
(*hash_it).second->squashed = true;
|
|
|
|
(*hash_it).second = NULL;
|
|
|
|
memDepHash.erase(hash_it);
|
|
#ifdef DEBUG
|
|
MemDepEntry::memdep_erase++;
|
|
#endif
|
|
|
|
instList[tid].erase(squash_it--);
|
|
}
|
|
|
|
// Tell the dependency predictor to squash as well.
|
|
depPred.squash(squashed_num, tid);
|
|
}
|
|
|
|
template <class MemDepPred, class Impl>
|
|
void
|
|
MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
|
|
DynInstPtr &violating_load)
|
|
{
|
|
DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
|
|
" load: %#x, store: %#x\n", violating_load->readPC(),
|
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store_inst->readPC());
|
|
// Tell the memory dependence unit of the violation.
|
|
depPred.violation(violating_load->readPC(), store_inst->readPC());
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|
}
|
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|
|
template <class MemDepPred, class Impl>
|
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void
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MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
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{
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DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
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inst->readPC(), inst->seqNum);
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depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
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}
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template <class MemDepPred, class Impl>
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inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
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MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
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{
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MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
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|
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assert(hash_it != memDepHash.end());
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|
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return (*hash_it).second;
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}
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template <class MemDepPred, class Impl>
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inline void
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MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
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{
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DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
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"to the ready list.\n", woken_inst_entry->inst->seqNum);
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|
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assert(!woken_inst_entry->squashed);
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|
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iqPtr->addReadyMemInst(woken_inst_entry->inst);
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}
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|
|
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template <class MemDepPred, class Impl>
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void
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MemDepUnit<MemDepPred, Impl>::dumpLists()
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|
{
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|
for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
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cprintf("Instruction list %i size: %i\n",
|
|
tid, instList[tid].size());
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|
|
|
ListIt inst_list_it = instList[tid].begin();
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int num = 0;
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|
|
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while (inst_list_it != instList[tid].end()) {
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cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
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|
"Squashed:%i\n\n",
|
|
num, (*inst_list_it)->readPC(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
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|
inst_list_it++;
|
|
++num;
|
|
}
|
|
}
|
|
|
|
cprintf("Memory dependence hash size: %i\n", memDepHash.size());
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|
|
|
#ifdef DEBUG
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|
cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
|
|
#endif
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|
}
|