850 lines
97 KiB
Text
850 lines
97 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.517355 # Number of seconds simulated
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sim_ticks 517355353500 # Number of ticks simulated
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final_tick 517355353500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 80961 # Simulator instruction rate (inst/s)
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host_op_rate 90318 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 27118174 # Simulator tick rate (ticks/s)
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host_mem_usage 288124 # Number of bytes of host memory used
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host_seconds 19077.81 # Real time elapsed on the host
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sim_insts 1544563023 # Number of instructions simulated
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sim_ops 1723073835 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 143726656 # Number of bytes read from this memory
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system.physmem.bytes_read::total 143774272 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 70431232 # Number of bytes written to this memory
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system.physmem.bytes_written::total 70431232 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2245729 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2246473 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1100488 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1100488 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 92037 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 277810319 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 277902357 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 92037 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 92037 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 136137051 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 136137051 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 136137051 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 92037 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 277810319 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 414039407 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 2246473 # Total number of read requests seen
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system.physmem.writeReqs 1100488 # Total number of write requests seen
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system.physmem.cpureqs 3346979 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 143774272 # Total number of bytes read from memory
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system.physmem.bytesWritten 70431232 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 143774272 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 70431232 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 670 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 141489 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 139656 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 141525 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 141936 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 142251 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 140152 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 141094 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 140745 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 138661 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 136342 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 140561 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 140724 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 141098 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 138976 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 138964 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 141629 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 69092 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 68439 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 69113 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 69523 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 69288 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 69039 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 68977 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 68383 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 67923 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 67021 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 69461 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 69311 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 69094 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 68543 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 68433 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 68848 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 18 # Number of times wr buffer was full causing retry
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system.physmem.totGap 517355284500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 2246473 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 1100488 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 1563773 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 450876 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 162701 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 68433 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 44051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 47144 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 47730 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 47800 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 47824 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 47829 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 47830 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 47829 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 47829 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 47847 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 3797 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 704 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 118 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 48 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
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system.physmem.totQLat 51860326500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 131350914000 # Sum of mem lat for all requests
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system.physmem.totBusLat 11229015000 # Total cycles spent in databus access
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system.physmem.totBankLat 68261572500 # Total cycles spent in bank access
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system.physmem.avgQLat 23092.11 # Average queueing delay per request
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system.physmem.avgBankLat 30395.17 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 58487.28 # Average memory access latency
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system.physmem.avgRdBW 277.90 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 277.90 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.23 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.25 # Average read queue length over time
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system.physmem.avgWrQLen 11.18 # Average write queue length over time
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system.physmem.readRowHits 827290 # Number of row buffer hits during reads
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system.physmem.writeRowHits 270800 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 24.61 # Row buffer hit rate for writes
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system.physmem.avgGap 154574.64 # Average gap between requests
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system.cpu.branchPred.lookups 303238356 # Number of BP lookups
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system.cpu.branchPred.condPredicted 249416285 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 15213179 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 173189005 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 161485027 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 93.242078 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 17562220 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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system.cpu.numCycles 1034710708 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 298243506 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2186139129 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 303238356 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 179047247 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 435102558 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 87842368 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 155357657 # Number of cycles fetch has spent blocked
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system.cpu.fetch.PendingTrapStallCycles 150 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 288597285 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 5732219 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 958597013 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.523325 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.213142 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 523494535 54.61% 54.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 25506855 2.66% 57.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 39100627 4.08% 61.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 48361324 5.05% 66.40% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 43019358 4.49% 70.88% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 46453211 4.85% 75.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 38427133 4.01% 79.74% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 18718773 1.95% 81.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 175515197 18.31% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 958597013 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.293066 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.112802 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 329802987 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 133619813 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 405201175 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 20080558 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 69892480 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 46072656 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 2366906963 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2456 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 69892480 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 353335624 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 63410713 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 18651 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 400220631 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 71718914 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 2304481635 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 133374 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 5031151 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 58581263 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 2279812946 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 10642278370 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 10642275398 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 2972 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 573493016 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 743 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 740 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 158758361 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 624481311 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 220974466 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 86299107 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 71333452 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2201408276 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 781 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2018173722 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 4013043 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 473803931 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1125355707 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 611 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 958597013 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.105341 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.906395 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 277575373 28.96% 28.96% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 151381497 15.79% 44.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 161170411 16.81% 61.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 119836935 12.50% 74.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 123952521 12.93% 86.99% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 73863494 7.71% 94.70% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 38468068 4.01% 98.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 9785076 1.02% 99.73% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2563638 0.27% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 958597013 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 884210 3.70% 3.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 5702 0.02% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 18296872 76.51% 80.23% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4728009 19.77% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1236704914 61.28% 61.28% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 925192 0.05% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 4 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 587491999 29.11% 90.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 193051561 9.57% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2018173722 # Type of FU issued
|
|
system.cpu.iq.rate 1.950471 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 23914793 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.011850 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5022872024 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2675402581 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1957467931 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2042088379 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 64652420 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 138554542 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 270922 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 192724 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 46127421 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4683320 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 69892480 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 28879520 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1498948 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2201409154 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 6144718 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 624481311 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 220974466 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 719 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 474123 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 89366 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 192724 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 8152988 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 9608721 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 17761709 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1988146149 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 573921356 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 30027573 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 97 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 764085836 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 238329441 # Number of branches executed
|
|
system.cpu.iew.exec_stores 190164480 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.921451 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1965914335 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1957468025 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1296382145 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2061123370 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.891802 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.628969 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 478433603 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 15212517 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 888704533 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.938860 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.728045 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 401292741 45.15% 45.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 192157168 21.62% 66.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 72538162 8.16% 74.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 35233922 3.96% 78.90% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 18967934 2.13% 81.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 30755514 3.46% 84.50% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 20061647 2.26% 86.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 11460153 1.29% 88.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106237292 11.95% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 888704533 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 660773814 # Number of memory references committed
|
|
system.cpu.commit.loads 485926769 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462426 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 106237292 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 2983974098 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4473052836 # The number of ROB writes
|
|
system.cpu.timesIdled 1016894 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 76113695 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.669905 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.669905 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.492749 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.492749 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 9956441643 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1937434969 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 88 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 99 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 737571197 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
|
|
system.cpu.icache.replacements 21 # number of replacements
|
|
system.cpu.icache.tagsinuse 624.513050 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 288596120 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 772 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 373829.170984 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 624.513050 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.304938 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.304938 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 288596120 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 288596120 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 288596120 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 288596120 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 288596120 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 288596120 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1165 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1165 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1165 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1165 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1165 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1165 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 63973500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 63973500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 63973500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 63973500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 63973500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 63973500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 288597285 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 288597285 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 288597285 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 288597285 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 288597285 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 288597285 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54912.875536 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 54912.875536 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54912.875536 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 54912.875536 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54912.875536 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 54912.875536 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 393 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 393 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 393 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 393 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 393 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 772 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 772 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 772 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45298000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 45298000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45298000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 45298000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45298000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 45298000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58676.165803 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58676.165803 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58676.165803 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 58676.165803 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58676.165803 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 58676.165803 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 2213784 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 31531.827043 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 9244985 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 2243559 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 4.120678 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 14438.568410 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 20.286933 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 17072.971700 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.440630 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.000619 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.521026 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.962275 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6287849 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6287876 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3781426 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3781426 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1066921 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1066921 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7354770 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7354797 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7354770 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7354797 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 745 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1419234 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1419979 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 826504 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 826504 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 745 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2245738 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 2246483 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 745 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2245738 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 2246483 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44250000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 113718707500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 113762957500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70604678000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 70604678000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 44250000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 184323385500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 184367635500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 44250000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 184323385500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 184367635500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 772 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7707083 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7707855 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3781426 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3781426 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893425 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1893425 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 772 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9600508 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9601280 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 772 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9600508 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9601280 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965026 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184147 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.184225 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436513 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436513 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965026 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233919 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.233977 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965026 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233919 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.233977 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59395.973154 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80126.820172 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80115.943616 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85425.694250 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85425.694250 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59395.973154 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82076.976700 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 82069.455010 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59395.973154 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82076.976700 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 82069.455010 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1100488 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1100488 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419225 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1419969 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826504 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 826504 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2245729 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 2246473 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2245729 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 2246473 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34695597 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96095078730 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96129774327 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60345956430 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60345956430 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34695597 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156441035160 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 156475730757 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34695597 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156441035160 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 156475730757 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963731 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184146 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184224 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436513 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436513 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963731 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.233976 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963731 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.233976 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46633.866935 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67709.544808 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67698.502099 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73013.508017 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73013.508017 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46633.866935 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69661.582123 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69653.955671 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46633.866935 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69661.582123 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69653.955671 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 9596411 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4088.019440 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 656077460 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 9600507 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 68.337793 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4088.019440 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 489029858 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 489029858 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 167047476 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 167047476 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 656077334 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 656077334 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 656077334 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 656077334 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 11474951 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 11474951 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5538571 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5538571 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 17013522 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 17013522 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 17013522 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 17013522 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 323064220500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 323064220500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 229479325824 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 229479325824 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 552543546324 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 552543546324 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 552543546324 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 552543546324 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 500504809 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 500504809 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 673090856 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 673090856 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 673090856 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 673090856 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022927 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022927 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025277 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.025277 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025277 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.025277 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28153.864927 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 28153.864927 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41432.948286 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 41432.948286 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 32476.729176 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 32476.729176 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 26385368 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 1054130 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1182490 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 64549 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.313396 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 16.330695 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3781426 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3781426 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767868 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 3767868 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645146 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3645146 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7413014 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7413014 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7413014 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7413014 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707083 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7707083 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893425 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1893425 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9600508 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9600508 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9600508 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9600508 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186133873500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 186133873500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83704359724 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83704359724 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269838233224 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 269838233224 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269838233224 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 269838233224 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24151.014528 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24151.014528 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44207.908802 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44207.908802 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|