gem5/configs/common
Akash Bagdia 7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
..
Benchmarks.py configs: add run scripts for ics/gb versions of android and bbench 2012-06-11 11:07:42 -04:00
CacheConfig.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
Caches.py config: Unify caches used in regressions and adjust L2 MSHRs 2012-10-30 07:44:08 -04:00
cpu2000.py cpu2000: Add missing art benchmark to all 2012-01-09 18:08:20 -06:00
CpuConfig.py config: Cleanup CPU configuration 2013-02-15 17:40:08 -05:00
FSConfig.py mem: Avoid explicitly zeroing the memory backing store 2013-05-30 12:53:54 -04:00
MemConfig.py mem: More descriptive DRAM config names 2013-05-30 12:54:14 -04:00
O3_ARM_v7a.py cpu: remove local/globalHistoryBits params from branch pred 2013-05-14 18:39:47 -04:00
Options.py config: Rename clock option to Ruby clock 2013-06-27 05:49:49 -04:00
Simulation.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
SysPaths.py make rcS files read from the m5 source directory, not /dist. 2006-11-08 14:10:25 -05:00