2a740aa096
This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
693 lines
21 KiB
C++
693 lines
21 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/pagetable_walker.hh"
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#include "arch/x86/tlb.hh"
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#include "arch/x86/vtophys.hh"
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#include "base/bitfield.hh"
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#include "base/trie.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/PageTableWalker.hh"
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#include "mem/packet_access.hh"
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#include "mem/request.hh"
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namespace X86ISA {
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// Unfortunately, the placement of the base field in a page table entry is
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// very erratic and would make a mess here. It might be moved here at some
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// point in the future.
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BitUnion64(PageTableEntry)
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Bitfield<63> nx;
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Bitfield<11, 9> avl;
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Bitfield<8> g;
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Bitfield<7> ps;
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Bitfield<6> d;
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Bitfield<5> a;
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Bitfield<4> pcd;
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Bitfield<3> pwt;
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Bitfield<2> u;
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Bitfield<1> w;
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Bitfield<0> p;
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EndBitUnion(PageTableEntry)
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Fault
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Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
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RequestPtr _req, BaseTLB::Mode _mode)
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{
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// TODO: in timing mode, instead of blocking when there are other
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// outstanding requests, see if this request can be coalesced with
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// another one (i.e. either coalesce or start walk)
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WalkerState * newState = new WalkerState(this, _translation, _req);
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newState->initState(_tc, _mode, sys->getMemoryMode() == Enums::timing);
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if (currStates.size()) {
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assert(newState->isTiming());
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DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
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currStates.push_back(newState);
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return NoFault;
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} else {
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currStates.push_back(newState);
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Fault fault = newState->startWalk();
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if (!newState->isTiming()) {
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currStates.pop_front();
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delete newState;
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}
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return fault;
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}
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}
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Fault
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Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
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BaseTLB::Mode _mode)
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{
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funcState.initState(_tc, _mode);
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return funcState.startFunctional(addr, logBytes);
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}
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bool
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Walker::WalkerPort::recvTimingResp(PacketPtr pkt)
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{
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return walker->recvTimingResp(pkt);
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}
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bool
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Walker::recvTimingResp(PacketPtr pkt)
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{
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WalkerSenderState * senderState =
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dynamic_cast<WalkerSenderState *>(pkt->senderState);
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pkt->senderState = senderState->saved;
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WalkerState * senderWalk = senderState->senderWalk;
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bool walkComplete = senderWalk->recvPacket(pkt);
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delete senderState;
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if (walkComplete) {
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std::list<WalkerState *>::iterator iter;
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for (iter = currStates.begin(); iter != currStates.end(); iter++) {
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WalkerState * walkerState = *(iter);
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if (walkerState == senderWalk) {
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iter = currStates.erase(iter);
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break;
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}
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}
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delete senderWalk;
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// Since we block requests when another is outstanding, we
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// need to check if there is a waiting request to be serviced
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if (currStates.size()) {
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WalkerState * newState = currStates.front();
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if (!newState->wasStarted())
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newState->startWalk();
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}
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}
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return true;
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}
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void
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Walker::WalkerPort::recvRetry()
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{
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walker->recvRetry();
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}
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void
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Walker::recvRetry()
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{
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std::list<WalkerState *>::iterator iter;
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for (iter = currStates.begin(); iter != currStates.end(); iter++) {
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WalkerState * walkerState = *(iter);
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if (walkerState->isRetrying()) {
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walkerState->retry();
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}
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}
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}
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bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
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{
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pkt->senderState = new WalkerSenderState(sendingState, pkt->senderState);
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return port.sendTimingReq(pkt);
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}
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BaseMasterPort &
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Walker::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "port")
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return port;
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else
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return MemObject::getMasterPort(if_name, idx);
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}
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void
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Walker::WalkerState::initState(ThreadContext * _tc,
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BaseTLB::Mode _mode, bool _isTiming)
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{
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assert(state == Ready);
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started = false;
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tc = _tc;
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mode = _mode;
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timing = _isTiming;
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}
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Fault
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Walker::WalkerState::startWalk()
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{
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Fault fault = NoFault;
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assert(started == false);
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started = true;
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setupWalk(req->getVaddr());
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if (timing) {
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nextState = state;
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state = Waiting;
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timingFault = NoFault;
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sendPackets();
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} else {
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do {
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walker->port.sendAtomic(read);
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PacketPtr write = NULL;
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fault = stepWalk(write);
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assert(fault == NoFault || read == NULL);
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state = nextState;
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nextState = Ready;
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if (write)
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walker->port.sendAtomic(write);
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} while(read);
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state = Ready;
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nextState = Waiting;
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}
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return fault;
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}
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Fault
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Walker::WalkerState::startFunctional(Addr &addr, unsigned &logBytes)
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{
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Fault fault = NoFault;
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assert(started == false);
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started = true;
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setupWalk(addr);
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do {
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walker->port.sendFunctional(read);
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// On a functional access (page table lookup), writes should
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// not happen so this pointer is ignored after stepWalk
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PacketPtr write = NULL;
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fault = stepWalk(write);
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assert(fault == NoFault || read == NULL);
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state = nextState;
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nextState = Ready;
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} while(read);
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logBytes = entry.logBytes;
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addr = entry.paddr;
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return fault;
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}
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Fault
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Walker::WalkerState::stepWalk(PacketPtr &write)
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{
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assert(state != Ready && state != Waiting);
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Fault fault = NoFault;
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write = NULL;
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PageTableEntry pte;
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if (dataSize == 8)
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pte = read->get<uint64_t>();
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else
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pte = read->get<uint32_t>();
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VAddr vaddr = entry.vaddr;
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bool uncacheable = pte.pcd;
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Addr nextRead = 0;
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bool doWrite = false;
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bool doTLBInsert = false;
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bool doEndWalk = false;
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bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
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switch(state) {
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case LongPML4:
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DPRINTF(PageTableWalker,
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"Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
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nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize;
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = pte.w;
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entry.user = pte.u;
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if (badNX || !pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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entry.noExec = pte.nx;
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nextState = LongPDP;
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break;
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case LongPDP:
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DPRINTF(PageTableWalker,
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"Got long mode PDP entry %#016x.\n", (uint64_t)pte);
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nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * dataSize;
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = entry.writable && pte.w;
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entry.user = entry.user && pte.u;
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if (badNX || !pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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nextState = LongPD;
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break;
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case LongPD:
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DPRINTF(PageTableWalker,
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"Got long mode PD entry %#016x.\n", (uint64_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = entry.writable && pte.w;
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entry.user = entry.user && pte.u;
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if (badNX || !pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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if (!pte.ps) {
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// 4 KB page
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entry.logBytes = 12;
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nextRead =
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((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
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nextState = LongPTE;
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break;
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} else {
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// 2 MB page
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entry.logBytes = 21;
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entry.paddr = (uint64_t)pte & (mask(31) << 21);
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entry.uncacheable = uncacheable;
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entry.global = pte.g;
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entry.patBit = bits(pte, 12);
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entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
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doTLBInsert = true;
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doEndWalk = true;
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break;
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}
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case LongPTE:
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DPRINTF(PageTableWalker,
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"Got long mode PTE entry %#016x.\n", (uint64_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = entry.writable && pte.w;
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entry.user = entry.user && pte.u;
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if (badNX || !pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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entry.paddr = (uint64_t)pte & (mask(40) << 12);
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entry.uncacheable = uncacheable;
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entry.global = pte.g;
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entry.patBit = bits(pte, 12);
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entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
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doTLBInsert = true;
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doEndWalk = true;
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break;
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case PAEPDP:
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DPRINTF(PageTableWalker,
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"Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
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nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * dataSize;
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if (!pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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nextState = PAEPD;
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break;
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case PAEPD:
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DPRINTF(PageTableWalker,
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"Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = pte.w;
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entry.user = pte.u;
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if (badNX || !pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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if (!pte.ps) {
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// 4 KB page
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entry.logBytes = 12;
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nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * dataSize;
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nextState = PAEPTE;
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break;
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} else {
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// 2 MB page
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entry.logBytes = 21;
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entry.paddr = (uint64_t)pte & (mask(31) << 21);
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entry.uncacheable = uncacheable;
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entry.global = pte.g;
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entry.patBit = bits(pte, 12);
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entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
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doTLBInsert = true;
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doEndWalk = true;
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break;
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}
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case PAEPTE:
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DPRINTF(PageTableWalker,
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"Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = entry.writable && pte.w;
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entry.user = entry.user && pte.u;
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if (badNX || !pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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entry.paddr = (uint64_t)pte & (mask(40) << 12);
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entry.uncacheable = uncacheable;
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entry.global = pte.g;
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entry.patBit = bits(pte, 7);
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entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
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doTLBInsert = true;
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doEndWalk = true;
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break;
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case PSEPD:
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DPRINTF(PageTableWalker,
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"Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = pte.w;
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entry.user = pte.u;
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if (!pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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if (!pte.ps) {
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// 4 KB page
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entry.logBytes = 12;
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nextRead =
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((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
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nextState = PTE;
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break;
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} else {
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// 4 MB page
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entry.logBytes = 21;
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entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
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entry.uncacheable = uncacheable;
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entry.global = pte.g;
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entry.patBit = bits(pte, 12);
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entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1);
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doTLBInsert = true;
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doEndWalk = true;
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break;
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}
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case PD:
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DPRINTF(PageTableWalker,
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"Got legacy mode PD entry %#08x.\n", (uint32_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = pte.w;
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entry.user = pte.u;
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if (!pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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// 4 KB page
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entry.logBytes = 12;
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nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
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nextState = PTE;
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break;
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case PTE:
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DPRINTF(PageTableWalker,
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"Got legacy mode PTE entry %#08x.\n", (uint32_t)pte);
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doWrite = !pte.a;
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pte.a = 1;
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entry.writable = pte.w;
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entry.user = pte.u;
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if (!pte.p) {
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doEndWalk = true;
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fault = pageFault(pte.p);
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break;
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}
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entry.paddr = (uint64_t)pte & (mask(20) << 12);
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entry.uncacheable = uncacheable;
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entry.global = pte.g;
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entry.patBit = bits(pte, 7);
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entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
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doTLBInsert = true;
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doEndWalk = true;
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break;
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default:
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panic("Unknown page table walker state %d!\n");
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}
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if (doEndWalk) {
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if (doTLBInsert)
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if (!functional)
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walker->tlb->insert(entry.vaddr, entry);
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endWalk();
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} else {
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PacketPtr oldRead = read;
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//If we didn't return, we're setting up another read.
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Request::Flags flags = oldRead->req->getFlags();
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flags.set(Request::UNCACHEABLE, uncacheable);
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RequestPtr request =
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new Request(nextRead, oldRead->getSize(), flags, walker->masterId);
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read = new Packet(request, MemCmd::ReadReq);
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read->allocate();
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// If we need to write, adjust the read packet to write the modified
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// value back to memory.
|
|
if (doWrite) {
|
|
write = oldRead;
|
|
write->set<uint64_t>(pte);
|
|
write->cmd = MemCmd::WriteReq;
|
|
write->clearDest();
|
|
} else {
|
|
write = NULL;
|
|
delete oldRead->req;
|
|
delete oldRead;
|
|
}
|
|
}
|
|
return fault;
|
|
}
|
|
|
|
void
|
|
Walker::WalkerState::endWalk()
|
|
{
|
|
nextState = Ready;
|
|
delete read->req;
|
|
delete read;
|
|
read = NULL;
|
|
}
|
|
|
|
void
|
|
Walker::WalkerState::setupWalk(Addr vaddr)
|
|
{
|
|
VAddr addr = vaddr;
|
|
CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
|
|
// Check if we're in long mode or not
|
|
Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
|
|
dataSize = 8;
|
|
Addr topAddr;
|
|
if (efer.lma) {
|
|
// Do long mode.
|
|
state = LongPML4;
|
|
topAddr = (cr3.longPdtb << 12) + addr.longl4 * dataSize;
|
|
enableNX = efer.nxe;
|
|
} else {
|
|
// We're in some flavor of legacy mode.
|
|
CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
|
|
if (cr4.pae) {
|
|
// Do legacy PAE.
|
|
state = PAEPDP;
|
|
topAddr = (cr3.paePdtb << 5) + addr.pael3 * dataSize;
|
|
enableNX = efer.nxe;
|
|
} else {
|
|
dataSize = 4;
|
|
topAddr = (cr3.pdtb << 12) + addr.norml2 * dataSize;
|
|
if (cr4.pse) {
|
|
// Do legacy PSE.
|
|
state = PSEPD;
|
|
} else {
|
|
// Do legacy non PSE.
|
|
state = PD;
|
|
}
|
|
enableNX = false;
|
|
}
|
|
}
|
|
|
|
nextState = Ready;
|
|
entry.vaddr = vaddr;
|
|
|
|
Request::Flags flags = Request::PHYSICAL;
|
|
if (cr3.pcd)
|
|
flags.set(Request::UNCACHEABLE);
|
|
RequestPtr request = new Request(topAddr, dataSize, flags,
|
|
walker->masterId);
|
|
read = new Packet(request, MemCmd::ReadReq);
|
|
read->allocate();
|
|
}
|
|
|
|
bool
|
|
Walker::WalkerState::recvPacket(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isResponse());
|
|
assert(inflight);
|
|
assert(state == Waiting);
|
|
assert(!read);
|
|
inflight--;
|
|
if (pkt->isRead()) {
|
|
state = nextState;
|
|
nextState = Ready;
|
|
PacketPtr write = NULL;
|
|
read = pkt;
|
|
timingFault = stepWalk(write);
|
|
state = Waiting;
|
|
assert(timingFault == NoFault || read == NULL);
|
|
if (write) {
|
|
writes.push_back(write);
|
|
}
|
|
sendPackets();
|
|
} else {
|
|
sendPackets();
|
|
}
|
|
if (inflight == 0 && read == NULL && writes.size() == 0) {
|
|
state = Ready;
|
|
nextState = Waiting;
|
|
if (timingFault == NoFault) {
|
|
/*
|
|
* Finish the translation. Now that we now the right entry is
|
|
* in the TLB, this should work with no memory accesses.
|
|
* There could be new faults unrelated to the table walk like
|
|
* permissions violations, so we'll need the return value as
|
|
* well.
|
|
*/
|
|
bool delayedResponse;
|
|
Fault fault = walker->tlb->translate(req, tc, NULL, mode,
|
|
delayedResponse, true);
|
|
assert(!delayedResponse);
|
|
// Let the CPU continue.
|
|
translation->finish(fault, req, tc, mode);
|
|
} else {
|
|
// There was a fault during the walk. Let the CPU know.
|
|
translation->finish(timingFault, req, tc, mode);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void
|
|
Walker::WalkerState::sendPackets()
|
|
{
|
|
//If we're already waiting for the port to become available, just return.
|
|
if (retrying)
|
|
return;
|
|
|
|
//Reads always have priority
|
|
if (read) {
|
|
PacketPtr pkt = read;
|
|
read = NULL;
|
|
inflight++;
|
|
if (!walker->sendTiming(this, pkt)) {
|
|
retrying = true;
|
|
read = pkt;
|
|
inflight--;
|
|
return;
|
|
}
|
|
}
|
|
//Send off as many of the writes as we can.
|
|
while (writes.size()) {
|
|
PacketPtr write = writes.back();
|
|
writes.pop_back();
|
|
inflight++;
|
|
if (!walker->sendTiming(this, write)) {
|
|
retrying = true;
|
|
writes.push_back(write);
|
|
inflight--;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool
|
|
Walker::WalkerState::isRetrying()
|
|
{
|
|
return retrying;
|
|
}
|
|
|
|
bool
|
|
Walker::WalkerState::isTiming()
|
|
{
|
|
return timing;
|
|
}
|
|
|
|
bool
|
|
Walker::WalkerState::wasStarted()
|
|
{
|
|
return started;
|
|
}
|
|
|
|
void
|
|
Walker::WalkerState::retry()
|
|
{
|
|
retrying = false;
|
|
sendPackets();
|
|
}
|
|
|
|
Fault
|
|
Walker::WalkerState::pageFault(bool present)
|
|
{
|
|
DPRINTF(PageTableWalker, "Raising page fault.\n");
|
|
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
|
|
if (mode == BaseTLB::Execute && !enableNX)
|
|
mode = BaseTLB::Read;
|
|
return new PageFault(entry.vaddr, present, mode, m5reg.cpl == 3, false);
|
|
}
|
|
|
|
/* end namespace X86ISA */ }
|
|
|
|
X86ISA::Walker *
|
|
X86PagetableWalkerParams::create()
|
|
{
|
|
return new X86ISA::Walker(this);
|
|
}
|