7b73c36f5d
There are some bits of some fields of the ExtMachInst which are not actually used for anything but are included in the hash of an ExtMachInst for simplicity and efficiency. This change makes sure the decoder's internal working ExtMachInst is completely initialized, even these unused bits, so that there isn't any nondeterministic behavior, no valgrind messages about uninitialized variables, and no potential false misses/redundant entries in the decode cache.
247 lines
7 KiB
C++
247 lines
7 KiB
C++
/*
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* Copyright (c) 2012 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_DECODER_HH__
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#define __ARCH_X86_DECODER_HH__
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#include <cassert>
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#include "arch/x86/regs/misc.hh"
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#include "arch/x86/types.hh"
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#include "base/bitfield.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/decode_cache.hh"
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#include "cpu/static_inst.hh"
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#include "debug/Decoder.hh"
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class ThreadContext;
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namespace X86ISA
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{
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class Decoder
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{
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private:
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//These are defined and documented in decoder_tables.cc
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static const uint8_t Prefixes[256];
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static const uint8_t UsesModRM[2][256];
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static const uint8_t ImmediateType[2][256];
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static const uint8_t SizeTypeToSize[3][10];
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protected:
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ThreadContext * tc;
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//The bytes to be predecoded
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MachInst fetchChunk;
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//The pc of the start of fetchChunk
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Addr basePC;
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//The pc the current instruction started at
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Addr origPC;
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//The offset into fetchChunk of current processing
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int offset;
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//The extended machine instruction being generated
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ExtMachInst emi;
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HandyM5Reg m5Reg;
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inline uint8_t getNextByte()
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{
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return ((uint8_t *)&fetchChunk)[offset];
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}
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void getImmediate(int &collected, uint64_t ¤t, int size)
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{
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//Figure out how many bytes we still need to get for the
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//immediate.
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int toGet = size - collected;
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//Figure out how many bytes are left in our "buffer"
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int remaining = sizeof(MachInst) - offset;
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//Get as much as we need, up to the amount available.
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toGet = toGet > remaining ? remaining : toGet;
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//Shift the bytes we want to be all the way to the right
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uint64_t partialImm = fetchChunk >> (offset * 8);
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//Mask off what we don't want
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partialImm &= mask(toGet * 8);
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//Shift it over to overlay with our displacement.
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partialImm <<= (immediateCollected * 8);
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//Put it into our displacement
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current |= partialImm;
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//Update how many bytes we've collected.
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collected += toGet;
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consumeBytes(toGet);
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}
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inline void consumeByte()
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{
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offset++;
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assert(offset <= sizeof(MachInst));
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if(offset == sizeof(MachInst))
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outOfBytes = true;
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}
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inline void consumeBytes(int numBytes)
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{
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offset += numBytes;
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assert(offset <= sizeof(MachInst));
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if(offset == sizeof(MachInst))
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outOfBytes = true;
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}
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void doReset();
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//State machine state
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protected:
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//Whether or not we're out of bytes
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bool outOfBytes;
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//Whether we've completed generating an ExtMachInst
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bool instDone;
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//The size of the displacement value
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int displacementSize;
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//The size of the immediate value
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int immediateSize;
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//This is how much of any immediate value we've gotten. This is used
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//for both the actual immediate and the displacement.
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int immediateCollected;
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enum State {
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ResetState,
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PrefixState,
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OpcodeState,
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ModRMState,
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SIBState,
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DisplacementState,
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ImmediateState,
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//We should never get to this state. Getting here is an error.
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ErrorState
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};
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State state;
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//Functions to handle each of the states
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State doPrefixState(uint8_t);
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State doOpcodeState(uint8_t);
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State doModRMState(uint8_t);
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State doSIBState(uint8_t);
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State doDisplacementState();
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State doImmediateState();
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public:
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Decoder(ThreadContext * _tc) :
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tc(_tc), basePC(0), origPC(0), offset(0),
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outOfBytes(true), instDone(false),
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state(ResetState)
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{
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memset(&emi, 0, sizeof(emi));
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emi.mode.mode = LongMode;
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emi.mode.submode = SixtyFourBitMode;
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m5Reg = 0;
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}
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void reset()
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{
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state = ResetState;
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}
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ThreadContext * getTC()
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{
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return tc;
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}
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void setTC(ThreadContext * _tc)
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{
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tc = _tc;
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}
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void process();
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//Use this to give data to the decoder. This should be used
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//when there is control flow.
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void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
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{
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DPRINTF(Decoder, "Getting more bytes.\n");
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basePC = fetchPC;
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offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
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fetchChunk = data;
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outOfBytes = false;
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process();
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}
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bool needMoreBytes()
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{
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return outOfBytes;
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}
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bool instReady()
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{
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return instDone;
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}
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void
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updateNPC(X86ISA::PCState &nextPC)
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{
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if (!nextPC.size()) {
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int size = basePC + offset - origPC;
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DPRINTF(Decoder,
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"Calculating the instruction size: "
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"basePC: %#x offset: %#x origPC: %#x size: %d\n",
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basePC, offset, origPC, size);
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nextPC.size(size);
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nextPC.npc(nextPC.pc() + size);
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}
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}
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protected:
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/// Caching for decoded instruction objects.
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static DecodeCache::InstMap instMap;
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static DecodeCache::AddrMap<StaticInstPtr> decodePages;
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public:
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StaticInstPtr decodeInst(ExtMachInst mach_inst);
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/// Decode a machine instruction.
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/// @param mach_inst The binary instruction to decode.
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/// @retval A pointer to the corresponding StaticInst object.
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StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
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StaticInstPtr
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decode(X86ISA::PCState &nextPC)
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{
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if (!instDone)
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return NULL;
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instDone = false;
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updateNPC(nextPC);
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return decode(emi, origPC);
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}
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};
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} // namespace X86ISA
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#endif // __ARCH_X86_DECODER_HH__
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