abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
379 lines
12 KiB
C++
379 lines
12 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* This device implemetns the niagara I/O bridge chip. It manages incomming
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* interrupts and posts them to the CPU when needed. It holds mask registers and
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* various status registers for CPUs to check what interrupts are pending as
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* well as facilities to send IPIs to other cpus.
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*/
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#include <cstring>
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/faults.hh"
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#include "base/trace.hh"
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#include "cpu/intr_control.hh"
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#include "dev/sparc/iob.hh"
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#include "dev/platform.hh"
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#include "mem/port.hh"
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#include "mem/packet_access.hh"
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#include "sim/faults.hh"
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#include "sim/system.hh"
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Iob::Iob(const Params *p)
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: PioDevice(p), ic(p->platform->intrctrl)
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{
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iobManAddr = ULL(0x9800000000);
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iobManSize = ULL(0x0100000000);
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iobJBusAddr = ULL(0x9F00000000);
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iobJBusSize = ULL(0x0100000000);
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assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
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// Get the interrupt controller from the platform
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ic = platform->intrctrl;
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for (int x = 0; x < NumDeviceIds; ++x) {
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intMan[x].cpu = 0;
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intMan[x].vector = 0;
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intCtl[x].mask = true;
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intCtl[x].pend = false;
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}
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}
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Tick
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Iob::read(PacketPtr pkt)
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{
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assert(pkt->result == Packet::Unknown);
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if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
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readIob(pkt);
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else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
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readJBus(pkt);
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else
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panic("Invalid address reached Iob\n");
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pkt->result = Packet::Success;
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return pioDelay;
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}
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void
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Iob::readIob(PacketPtr pkt)
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{
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Addr accessAddr = pkt->getAddr() - iobManAddr;
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int index;
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uint64_t data;
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if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
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index = (accessAddr - IntManAddr) >> 3;
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data = intMan[index].cpu << 8 | intMan[index].vector << 0;
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pkt->set(data);
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return;
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}
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if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
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index = (accessAddr - IntManAddr) >> 3;
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data = intCtl[index].mask ? 1 << 2 : 0 |
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intCtl[index].pend ? 1 << 0 : 0;
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pkt->set(data);
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return;
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}
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if (accessAddr == JIntVecAddr) {
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pkt->set(jIntVec);
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return;
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}
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panic("Read to unknown IOB offset 0x%x\n", accessAddr);
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}
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void
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Iob::readJBus(PacketPtr pkt)
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{
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Addr accessAddr = pkt->getAddr() - iobJBusAddr;
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int cpuid = pkt->req->getCpuNum();
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int index;
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uint64_t data;
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if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) {
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index = (accessAddr - JIntData0Addr) >> 3;
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pkt->set(jBusData0[index]);
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return;
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}
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if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) {
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index = (accessAddr - JIntData1Addr) >> 3;
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pkt->set(jBusData1[index]);
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return;
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}
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if (accessAddr == JIntDataA0Addr) {
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pkt->set(jBusData0[cpuid]);
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return;
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}
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if (accessAddr == JIntDataA1Addr) {
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pkt->set(jBusData1[cpuid]);
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return;
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}
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if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
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index = (accessAddr - JIntBusyAddr) >> 3;
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data = jIntBusy[index].busy ? 1 << 5 : 0 |
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jIntBusy[index].source;
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pkt->set(data);
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return;
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}
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if (accessAddr == JIntABusyAddr) {
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data = jIntBusy[cpuid].busy ? 1 << 5 : 0 |
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jIntBusy[cpuid].source;
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pkt->set(data);
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return;
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};
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panic("Read to unknown JBus offset 0x%x\n", accessAddr);
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}
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Tick
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Iob::write(PacketPtr pkt)
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{
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if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize)
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writeIob(pkt);
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else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize)
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writeJBus(pkt);
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else
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panic("Invalid address reached Iob\n");
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pkt->result = Packet::Success;
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return pioDelay;
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}
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void
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Iob::writeIob(PacketPtr pkt)
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{
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Addr accessAddr = pkt->getAddr() - iobManAddr;
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int index;
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uint64_t data;
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if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
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index = (accessAddr - IntManAddr) >> 3;
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data = pkt->get<uint64_t>();
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intMan[index].cpu = bits(data,12,8);
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intMan[index].vector = bits(data,5,0);
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DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index,
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intMan[index].cpu, intMan[index].vector);
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return;
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}
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if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) {
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index = (accessAddr - IntManAddr) >> 3;
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data = pkt->get<uint64_t>();
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intCtl[index].mask = bits(data,2,2);
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if (bits(data,1,1))
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intCtl[index].pend = false;
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DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index,
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intCtl[index].pend, bits(data,2,2));
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return;
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}
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if (accessAddr == JIntVecAddr) {
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jIntVec = bits(pkt->get<uint64_t>(), 5,0);
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DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec);
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return;
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}
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if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) {
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Type type;
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int cpu_id;
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int vector;
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index = (accessAddr - IntManAddr) >> 3;
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data = pkt->get<uint64_t>();
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type = (Type)bits(data,17,16);
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cpu_id = bits(data, 12,8);
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vector = bits(data,5,0);
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generateIpi(type,cpu_id, vector);
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return;
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}
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panic("Write to unknown IOB offset 0x%x\n", accessAddr);
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}
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void
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Iob::writeJBus(PacketPtr pkt)
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{
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Addr accessAddr = pkt->getAddr() - iobJBusAddr;
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int cpuid = pkt->req->getCpuNum();
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int index;
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uint64_t data;
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if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) {
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index = (accessAddr - JIntBusyAddr) >> 3;
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data = pkt->get<uint64_t>();
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jIntBusy[index].busy = bits(data,5,5);
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DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index,
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jIntBusy[index].busy);
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return;
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}
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if (accessAddr == JIntABusyAddr) {
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data = pkt->get<uint64_t>();
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jIntBusy[cpuid].busy = bits(data,5,5);
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DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid,
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jIntBusy[cpuid].busy);
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return;
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};
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panic("Write to unknown JBus offset 0x%x\n", accessAddr);
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}
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void
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Iob::receiveDeviceInterrupt(DeviceId devid)
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{
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assert(devid < NumDeviceIds);
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if (intCtl[devid].mask)
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return;
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intCtl[devid].mask = true;
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intCtl[devid].pend = true;
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DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n",
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devid, intMan[devid].cpu, intMan[devid].vector);
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ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
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}
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void
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Iob::generateIpi(Type type, int cpu_id, int vector)
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{
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SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
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if (cpu_id >= sys->getNumCPUs())
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return;
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switch (type) {
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case 0: // interrupt
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DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n",
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cpu_id, vector);
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ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
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break;
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case 1: // reset
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warn("Sending reset to CPU: %d\n", cpu_id);
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if (vector != por->trapType())
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panic("Don't know how to set non-POR reset to cpu\n");
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por->invoke(sys->threadContexts[cpu_id]);
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sys->threadContexts[cpu_id]->activate();
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break;
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case 2: // idle -- this means stop executing and don't wake on interrupts
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DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
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sys->threadContexts[cpu_id]->halt();
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break;
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case 3: // resume
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DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
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sys->threadContexts[cpu_id]->activate();
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break;
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default:
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panic("Invalid type to generate ipi\n");
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}
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}
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bool
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Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1)
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{
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// If we are already dealing with an interrupt for that cpu we can't deal
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// with another one right now... come back later
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if (jIntBusy[cpu_id].busy)
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return false;
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DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n",
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source, cpu_id, jIntVec);
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jIntBusy[cpu_id].busy = true;
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jIntBusy[cpu_id].source = source;
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jBusData0[cpu_id] = d0;
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jBusData1[cpu_id] = d1;
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ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec);
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return true;
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}
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void
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Iob::addressRanges(AddrRangeList &range_list)
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{
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range_list.clear();
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range_list.push_back(RangeSize(iobManAddr, iobManSize));
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range_list.push_back(RangeSize(iobJBusAddr, iobJBusSize));
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}
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void
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Iob::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(jIntVec);
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SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs);
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SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs);
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for (int x = 0; x < NumDeviceIds; x++) {
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nameOut(os, csprintf("%s.Int%d", name(), x));
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paramOut(os, "cpu", intMan[x].cpu);
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paramOut(os, "vector", intMan[x].vector);
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paramOut(os, "mask", intCtl[x].mask);
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paramOut(os, "pend", intCtl[x].pend);
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};
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for (int x = 0; x < MaxNiagaraProcs; x++) {
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nameOut(os, csprintf("%s.jIntBusy%d", name(), x));
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paramOut(os, "busy", jIntBusy[x].busy);
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paramOut(os, "source", jIntBusy[x].source);
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};
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}
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void
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Iob::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(jIntVec);
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UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs);
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UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs);
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for (int x = 0; x < NumDeviceIds; x++) {
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paramIn(cp, csprintf("%s.Int%d", name(), x), "cpu", intMan[x].cpu);
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paramIn(cp, csprintf("%s.Int%d", name(), x), "vector", intMan[x].vector);
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paramIn(cp, csprintf("%s.Int%d", name(), x), "mask", intCtl[x].mask);
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paramIn(cp, csprintf("%s.Int%d", name(), x), "pend", intCtl[x].pend);
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};
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for (int x = 0; x < MaxNiagaraProcs; x++) {
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paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "busy", jIntBusy[x].busy);
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paramIn(cp, csprintf("%s.jIntBusy%d", name(), x), "source", jIntBusy[x].source);
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};
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}
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Iob *
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IobParams::create()
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{
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return new Iob(this);
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}
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