the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
135 lines
5.5 KiB
Python
135 lines
5.5 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#
|
|
# Authors: Gabe Black
|
|
|
|
from m5.params import *
|
|
from m5.proxy import *
|
|
from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
|
|
from Uart import Uart8250
|
|
from Platform import Platform
|
|
from SimConsole import SimConsole
|
|
|
|
|
|
class MmDisk(BasicPioDevice):
|
|
type = 'MmDisk'
|
|
image = Param.DiskImage("Disk Image")
|
|
pio_addr = 0x1F40000000
|
|
|
|
class DumbTOD(BasicPioDevice):
|
|
type = 'DumbTOD'
|
|
time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
|
|
pio_addr = 0xfff0c1fff8
|
|
|
|
class Iob(PioDevice):
|
|
type = 'Iob'
|
|
pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
|
|
|
|
|
|
class T1000(Platform):
|
|
type = 'T1000'
|
|
system = Param.System(Parent.any, "system")
|
|
|
|
fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
|
|
#warn_access="Accessing Clock Unit -- Unimplemented!")
|
|
|
|
fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
|
|
ret_data64=0x0000000000000000, update_data=False)
|
|
#warn_access="Accessing Memory Banks -- Unimplemented!")
|
|
|
|
fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
|
|
#warn_access="Accessing JBI -- Unimplemented!")
|
|
|
|
fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
|
|
ret_data64=0x0000000000000001, update_data=True)
|
|
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
|
|
ret_data64=0x0000000000000001, update_data=True)
|
|
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
|
|
ret_data64=0x0000000000000001, update_data=True)
|
|
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
|
|
ret_data64=0x0000000000000001, update_data=True)
|
|
#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
|
|
ret_data64=0x0000000000000000, update_data=True)
|
|
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
|
|
ret_data64=0x0000000000000000, update_data=True)
|
|
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
|
|
ret_data64=0x0000000000000000, update_data=True)
|
|
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
|
|
|
fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
|
|
ret_data64=0x0000000000000000, update_data=True)
|
|
#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
|
|
|
|
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
|
|
#warn_access="Accessing SSI -- Unimplemented!")
|
|
|
|
hconsole = SimConsole()
|
|
hvuart = Uart8250(pio_addr=0xfff0c2c000)
|
|
htod = DumbTOD()
|
|
|
|
pconsole = SimConsole()
|
|
puart0 = Uart8250(pio_addr=0x1f10000000)
|
|
|
|
iob = Iob()
|
|
# Attach I/O devices that are on chip
|
|
def attachOnChipIO(self, bus):
|
|
self.iob.pio = bus.port
|
|
self.htod.pio = bus.port
|
|
|
|
|
|
# Attach I/O devices to specified bus object. Can't do this
|
|
# earlier, since the bus object itself is typically defined at the
|
|
# System level.
|
|
def attachIO(self, bus):
|
|
self.hvuart.sim_console = self.hconsole
|
|
self.puart0.sim_console = self.pconsole
|
|
self.fake_clk.pio = bus.port
|
|
self.fake_membnks.pio = bus.port
|
|
self.fake_l2_1.pio = bus.port
|
|
self.fake_l2_2.pio = bus.port
|
|
self.fake_l2_3.pio = bus.port
|
|
self.fake_l2_4.pio = bus.port
|
|
self.fake_l2esr_1.pio = bus.port
|
|
self.fake_l2esr_2.pio = bus.port
|
|
self.fake_l2esr_3.pio = bus.port
|
|
self.fake_l2esr_4.pio = bus.port
|
|
self.fake_ssi.pio = bus.port
|
|
self.fake_jbi.pio = bus.port
|
|
self.puart0.pio = bus.port
|
|
self.hvuart.pio = bus.port
|