abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
236 lines
7 KiB
C++
236 lines
7 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Schultz
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* Miguel Serrano
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*/
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/** @file
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* Simple PCI IDE controller with bus mastering capability and UDMA
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* modeled after controller in the Intel PIIX4 chip
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*/
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#ifndef __IDE_CTRL_HH__
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#define __IDE_CTRL_HH__
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#include "dev/pcidev.hh"
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#include "dev/pcireg.h"
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#include "dev/io_device.hh"
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#include "params/IdeController.hh"
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#define BMIC0 0x0 // Bus master IDE command register
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#define BMIS0 0x2 // Bus master IDE status register
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#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
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#define BMIC1 0x8 // Bus master IDE command register
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#define BMIS1 0xa // Bus master IDE status register
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#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
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// Bus master IDE command register bit fields
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#define RWCON 0x08 // Bus master read/write control
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#define SSBM 0x01 // Start/stop bus master
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// Bus master IDE status register bit fields
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#define DMA1CAP 0x40 // Drive 1 DMA capable
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#define DMA0CAP 0x20 // Drive 0 DMA capable
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#define IDEINTS 0x04 // IDE Interrupt Status
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#define IDEDMAE 0x02 // IDE DMA error
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#define BMIDEA 0x01 // Bus master IDE active
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// IDE Command byte fields
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#define IDE_SELECT_OFFSET (6)
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#define IDE_SELECT_DEV_BIT 0x10
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#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
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#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
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// IDE Timing Register bit fields
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#define IDETIM_DECODE_EN 0x8000
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// PCI device specific register byte offsets
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#define IDE_CTRL_CONF_START 0x40
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#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
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#define IDE_CTRL_CONF_PRIM_TIMING 0x40
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#define IDE_CTRL_CONF_SEC_TIMING 0x42
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#define IDE_CTRL_CONF_DEV_TIMING 0x44
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#define IDE_CTRL_CONF_UDMA_CNTRL 0x48
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#define IDE_CTRL_CONF_UDMA_TIMING 0x4A
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#define IDE_CTRL_CONF_IDE_CONFIG 0x54
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enum IdeRegType {
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COMMAND_BLOCK,
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CONTROL_BLOCK,
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BMI_BLOCK
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};
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class IdeDisk;
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class IntrControl;
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class PciConfigAll;
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class Platform;
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/**
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* Device model for an Intel PIIX4 IDE controller
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*/
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class IdeController : public PciDev
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{
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friend class IdeDisk;
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enum IdeChannel {
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PRIMARY = 0,
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SECONDARY = 1
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};
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private:
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/** Primary command block registers */
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Addr pri_cmd_addr;
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Addr pri_cmd_size;
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/** Primary control block registers */
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Addr pri_ctrl_addr;
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Addr pri_ctrl_size;
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/** Secondary command block registers */
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Addr sec_cmd_addr;
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Addr sec_cmd_size;
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/** Secondary control block registers */
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Addr sec_ctrl_addr;
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Addr sec_ctrl_size;
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/** Bus master interface (BMI) registers */
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Addr bmi_addr;
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Addr bmi_size;
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private:
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/** Registers used for bus master interface */
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union {
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uint8_t data[16];
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struct {
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uint8_t bmic0;
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uint8_t reserved_0;
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uint8_t bmis0;
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uint8_t reserved_1;
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uint32_t bmidtp0;
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uint8_t bmic1;
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uint8_t reserved_2;
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uint8_t bmis1;
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uint8_t reserved_3;
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uint32_t bmidtp1;
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};
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struct {
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uint8_t bmic;
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uint8_t reserved_4;
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uint8_t bmis;
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uint8_t reserved_5;
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uint32_t bmidtp;
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} chan[2];
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} bmi_regs;
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/** Shadows of the device select bit */
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uint8_t dev[2];
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/** Registers used in device specific PCI configuration */
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union {
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uint8_t data[22];
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struct {
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uint16_t idetim0;
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uint16_t idetim1;
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uint8_t sidetim;
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uint8_t reserved_0[3];
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uint8_t udmactl;
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uint8_t reserved_1;
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uint16_t udmatim;
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uint8_t reserved_2[8];
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uint16_t ideconfig;
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};
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} config_regs;
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// Internal management variables
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bool io_enabled;
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bool bm_enabled;
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bool cmd_in_progress[4];
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private:
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/** IDE disks connected to controller */
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IdeDisk *disks[4];
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private:
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/** Parse the access address to pass on to device */
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void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
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IdeRegType ®_type);
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/** Select the disk based on the channel and device bit */
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int getDisk(IdeChannel channel);
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/** Select the disk based on a pointer */
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int getDisk(IdeDisk *diskPtr);
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public:
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/** See if a disk is selected based on its pointer */
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bool isDiskSelected(IdeDisk *diskPtr);
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public:
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typedef IdeControllerParams Params;
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const Params *params() const { return (const Params *)_params; }
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IdeController(Params *p);
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~IdeController();
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virtual Tick writeConfig(PacketPtr pkt);
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virtual Tick readConfig(PacketPtr pkt);
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void setDmaComplete(IdeDisk *disk);
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/**
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* Read a done field for a given target.
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* @param pkt Packet describing what is to be read
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* @return The amount of time to complete this request
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*/
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virtual Tick read(PacketPtr pkt);
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/**
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* Write a done field for a given target.
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* @param pkt Packet describing what is to be written
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* @return The amount of time to complete this request
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*/
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virtual Tick write(PacketPtr pkt);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __IDE_CTRL_HH_
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