abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
638 lines
20 KiB
C++
638 lines
20 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's 8254x line of gigabit ethernet controllers.
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*/
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#ifndef __DEV_I8254XGBE_HH__
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#define __DEV_I8254XGBE_HH__
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#include <deque>
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#include <string>
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#include "base/inet.hh"
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#include "base/statistics.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/i8254xGBe_defs.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "params/IGbE.hh"
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#include "sim/eventq.hh"
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class IGbEInt;
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class IGbE : public PciDev
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{
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private:
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IGbEInt *etherInt;
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// device registers
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iGbReg::Regs regs;
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// eeprom data, status and control bits
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int eeOpBits, eeAddrBits, eeDataBits;
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uint8_t eeOpcode, eeAddr;
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uint16_t flash[iGbReg::EEPROM_SIZE];
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// The drain event if we have one
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Event *drainEvent;
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// cached parameters from params struct
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bool useFlowControl;
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// packet fifos
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PacketFifo rxFifo;
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PacketFifo txFifo;
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// Packet that we are currently putting into the txFifo
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EthPacketPtr txPacket;
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// Should to Rx/Tx State machine tick?
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bool rxTick;
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bool txTick;
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bool txFifoTick;
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bool rxDmaPacket;
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// Event and function to deal with RDTR timer expiring
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void rdtrProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n");
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postInterrupt(iGbReg::IT_RXT, true);
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}
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//friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
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EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
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// Event and function to deal with RADV timer expiring
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void radvProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n");
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postInterrupt(iGbReg::IT_RXT, true);
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}
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//friend class EventWrapper<IGbE, &IGbE::radvProcess>;
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EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
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// Event and function to deal with TADV timer expiring
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void tadvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW, true);
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}
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//friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
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EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
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// Event and function to deal with TIDV timer expiring
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void tidvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW, true);
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}
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//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
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EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
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// Main event to tick the device
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void tick();
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//friend class EventWrapper<IGbE, &IGbE::tick>;
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EventWrapper<IGbE, &IGbE::tick> tickEvent;
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void rxStateMachine();
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void txStateMachine();
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void txWire();
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/** Write an interrupt into the interrupt pending register and check mask
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* and interrupt limit timer before sending interrupt to CPU
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* @param t the type of interrupt we are posting
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* @param now should we ignore the interrupt limiting timer
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*/
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void postInterrupt(iGbReg::IntTypes t, bool now = false);
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/** Check and see if changes to the mask register have caused an interrupt
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* to need to be sent or perhaps removed an interrupt cause.
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*/
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void chkInterrupt();
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/** Send an interrupt to the cpu
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*/
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void cpuPostInt();
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// Event to moderate interrupts
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EventWrapper<IGbE, &IGbE::cpuPostInt> interEvent;
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/** Clear the interupt line to the cpu
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*/
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void cpuClearInt();
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Tick intClock() { return Clock::Int::ns * 1024; }
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/** This function is used to restart the clock so it can handle things like
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* draining and resume in one place. */
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void restartClock();
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/** Check if all the draining things that need to occur have occured and
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* handle the drain event if so.
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*/
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void checkDrain();
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template<class T>
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class DescCache
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{
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protected:
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virtual Addr descBase() const = 0;
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virtual long descHead() const = 0;
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virtual long descTail() const = 0;
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virtual long descLen() const = 0;
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virtual void updateHead(long h) = 0;
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virtual void enableSm() = 0;
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virtual void intAfterWb() const {}
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std::deque<T*> usedCache;
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std::deque<T*> unusedCache;
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T *fetchBuf;
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T *wbBuf;
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// Pointer to the device we cache for
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IGbE *igbe;
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// Name of this descriptor cache
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std::string _name;
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// How far we've cached
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int cachePnt;
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// The size of the descriptor cache
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int size;
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// How many descriptors we are currently fetching
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int curFetching;
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// How many descriptors we are currently writing back
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int wbOut;
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// if the we wrote back to the end of the descriptor ring and are going
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// to have to wrap and write more
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bool moreToWb;
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// What the alignment is of the next descriptor writeback
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Addr wbAlignment;
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/** The packet that is currently being dmad to memory if any
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*/
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EthPacketPtr pktPtr;
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public:
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DescCache(IGbE *i, const std::string n, int s)
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: igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), wbOut(0),
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pktPtr(NULL), fetchEvent(this), wbEvent(this)
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{
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fetchBuf = new T[size];
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wbBuf = new T[size];
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}
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virtual ~DescCache()
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{
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reset();
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}
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std::string name() { return _name; }
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/** If the address/len/head change when we've got descriptors that are
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* dirty that is very bad. This function checks that we don't and if we
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* do panics.
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*/
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void areaChanged()
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{
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if (usedCache.size() > 0 || curFetching || wbOut)
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panic("Descriptor Address, Length or Head changed. Bad\n");
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reset();
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}
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void writeback(Addr aMask)
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{
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int curHead = descHead();
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int max_to_wb = usedCache.size();
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DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
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"%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
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curHead, descTail(), descLen(), cachePnt, max_to_wb,
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descLeft());
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// Check if this writeback is less restrictive that the previous
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// and if so setup another one immediately following it
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if (wbOut && (aMask < wbAlignment)) {
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moreToWb = true;
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wbAlignment = aMask;
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DPRINTF(EthernetDesc, "Writing back already in process, returning\n");
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return;
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}
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moreToWb = false;
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wbAlignment = aMask;
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if (max_to_wb + curHead >= descLen()) {
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max_to_wb = descLen() - curHead;
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moreToWb = true;
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// this is by definition aligned correctly
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} else if (aMask != 0) {
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// align the wb point to the mask
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max_to_wb = max_to_wb & ~aMask;
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}
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DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
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if (max_to_wb <= 0 || wbOut)
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return;
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wbOut = max_to_wb;
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for (int x = 0; x < wbOut; x++)
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memcpy(&wbBuf[x], usedCache[x], sizeof(T));
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for (int x = 0; x < wbOut; x++) {
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assert(usedCache.size());
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delete usedCache[0];
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usedCache.pop_front();
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};
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assert(wbOut);
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igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
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wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf);
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}
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/** Fetch a chunk of descriptors into the descriptor cache.
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* Calls fetchComplete when the memory system returns the data
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*/
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void fetchDescriptors()
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{
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size_t max_to_fetch;
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if (descTail() >= cachePnt)
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max_to_fetch = descTail() - cachePnt;
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else
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max_to_fetch = descLen() - cachePnt;
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max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
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unusedCache.size()));
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DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
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"%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
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descHead(), descTail(), descLen(), cachePnt,
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max_to_fetch, descLeft());
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// Nothing to do
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if (max_to_fetch == 0 || curFetching)
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return;
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// So we don't have two descriptor fetches going on at once
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curFetching = max_to_fetch;
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DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
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descBase() + cachePnt * sizeof(T),
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igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
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curFetching * sizeof(T));
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assert(curFetching);
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igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
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curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf);
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}
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/** Called by event when dma to read descriptors is completed
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*/
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void fetchComplete()
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{
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T *newDesc;
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for (int x = 0; x < curFetching; x++) {
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newDesc = new T;
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memcpy(newDesc, &fetchBuf[x], sizeof(T));
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unusedCache.push_back(newDesc);
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}
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#ifndef NDEBUG
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int oldCp = cachePnt;
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#endif
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cachePnt += curFetching;
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assert(cachePnt <= descLen());
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if (cachePnt == descLen())
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cachePnt = 0;
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curFetching = 0;
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DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n",
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oldCp, cachePnt);
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enableSm();
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igbe->checkDrain();
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}
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EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
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/** Called by event when dma to writeback descriptors is completed
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*/
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void wbComplete()
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{
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long curHead = descHead();
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#ifndef NDEBUG
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long oldHead = curHead;
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#endif
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curHead += wbOut;
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wbOut = 0;
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if (curHead >= descLen())
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curHead -= descLen();
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// Update the head
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updateHead(curHead);
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DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n",
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oldHead, curHead);
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// If we still have more to wb, call wb now
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if (moreToWb) {
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DPRINTF(EthernetDesc, "Writeback has more todo\n");
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writeback(wbAlignment);
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}
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intAfterWb();
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igbe->checkDrain();
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}
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EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
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/* Return the number of descriptors left in the ring, so the device has
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* a way to figure out if it needs to interrupt.
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*/
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int descLeft() const
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{
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int left = unusedCache.size();
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if (cachePnt - descTail() >= 0)
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left += (cachePnt - descTail());
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else
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left += (descTail() - cachePnt);
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return left;
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}
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/* Return the number of descriptors used and not written back.
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*/
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int descUsed() const { return usedCache.size(); }
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/* Return the number of cache unused descriptors we have. */
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int descUnused() const {return unusedCache.size(); }
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/* Get into a state where the descriptor address/head/etc colud be
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* changed */
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void reset()
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{
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DPRINTF(EthernetDesc, "Reseting descriptor cache\n");
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for (int x = 0; x < usedCache.size(); x++)
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delete usedCache[x];
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for (int x = 0; x < unusedCache.size(); x++)
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delete unusedCache[x];
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usedCache.clear();
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unusedCache.clear();
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cachePnt = 0;
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}
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virtual void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(cachePnt);
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SERIALIZE_SCALAR(curFetching);
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SERIALIZE_SCALAR(wbOut);
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SERIALIZE_SCALAR(moreToWb);
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SERIALIZE_SCALAR(wbAlignment);
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int usedCacheSize = usedCache.size();
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SERIALIZE_SCALAR(usedCacheSize);
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for(int x = 0; x < usedCacheSize; x++) {
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arrayParamOut(os, csprintf("usedCache_%d", x),
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(uint8_t*)usedCache[x],sizeof(T));
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}
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int unusedCacheSize = unusedCache.size();
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SERIALIZE_SCALAR(unusedCacheSize);
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for(int x = 0; x < unusedCacheSize; x++) {
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arrayParamOut(os, csprintf("unusedCache_%d", x),
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(uint8_t*)unusedCache[x],sizeof(T));
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}
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}
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virtual void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(cachePnt);
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UNSERIALIZE_SCALAR(curFetching);
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UNSERIALIZE_SCALAR(wbOut);
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UNSERIALIZE_SCALAR(moreToWb);
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UNSERIALIZE_SCALAR(wbAlignment);
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int usedCacheSize;
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UNSERIALIZE_SCALAR(usedCacheSize);
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T *temp;
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for(int x = 0; x < usedCacheSize; x++) {
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temp = new T;
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arrayParamIn(cp, section, csprintf("usedCache_%d", x),
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(uint8_t*)temp,sizeof(T));
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usedCache.push_back(temp);
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}
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int unusedCacheSize;
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UNSERIALIZE_SCALAR(unusedCacheSize);
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for(int x = 0; x < unusedCacheSize; x++) {
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temp = new T;
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arrayParamIn(cp, section, csprintf("unusedCache_%d", x),
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(uint8_t*)temp,sizeof(T));
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unusedCache.push_back(temp);
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}
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}
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virtual bool hasOutstandingEvents() {
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return wbEvent.scheduled() || fetchEvent.scheduled();
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}
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};
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class RxDescCache : public DescCache<iGbReg::RxDesc>
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{
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protected:
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virtual Addr descBase() const { return igbe->regs.rdba(); }
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virtual long descHead() const { return igbe->regs.rdh(); }
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virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
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virtual long descTail() const { return igbe->regs.rdt(); }
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virtual void updateHead(long h) { igbe->regs.rdh(h); }
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virtual void enableSm();
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bool pktDone;
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public:
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RxDescCache(IGbE *i, std::string n, int s);
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/** Write the given packet into the buffer(s) pointed to by the
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* descriptor and update the book keeping. Should only be called when
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* there are no dma's pending.
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* @param packet ethernet packet to write
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* @return if the packet could be written (there was a free descriptor)
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*/
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bool writePacket(EthPacketPtr packet);
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/** Called by event when dma to write packet is completed
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*/
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void pktComplete();
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/** Check if the dma on the packet has completed.
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*/
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bool packetDone();
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EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
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virtual bool hasOutstandingEvents();
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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friend class RxDescCache;
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RxDescCache rxDescCache;
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class TxDescCache : public DescCache<iGbReg::TxDesc>
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{
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protected:
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virtual Addr descBase() const { return igbe->regs.tdba(); }
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virtual long descHead() const { return igbe->regs.tdh(); }
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virtual long descTail() const { return igbe->regs.tdt(); }
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virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
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virtual void updateHead(long h) { igbe->regs.tdh(h); }
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virtual void enableSm();
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virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW);}
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bool pktDone;
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bool isTcp;
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bool pktWaiting;
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public:
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TxDescCache(IGbE *i, std::string n, int s);
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/** Tell the cache to DMA a packet from main memory into its buffer and
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* return the size the of the packet to reserve space in tx fifo.
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* @return size of the packet
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*/
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int getPacketSize();
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void getPacketData(EthPacketPtr p);
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/** Ask if the packet has been transfered so the state machine can give
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* it to the fifo.
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* @return packet available in descriptor cache
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*/
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bool packetAvailable();
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/** Ask if we are still waiting for the packet to be transfered.
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* @return packet still in transit.
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*/
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bool packetWaiting() { return pktWaiting; }
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/** Called by event when dma to write packet is completed
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*/
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void pktComplete();
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EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
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virtual bool hasOutstandingEvents();
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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friend class TxDescCache;
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TxDescCache txDescCache;
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public:
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typedef IGbEParams Params;
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const Params *
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params() const
|
|
{
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return dynamic_cast<const Params *>(_params);
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}
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IGbE(Params *params);
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~IGbE() {}
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|
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Tick clock;
|
|
inline Tick cycles(int numCycles) const { return numCycles * clock; }
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|
|
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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|
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virtual Tick writeConfig(PacketPtr pkt);
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|
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bool ethRxPkt(EthPacketPtr packet);
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void ethTxDone();
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void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
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|
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
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virtual unsigned int drain(Event *de);
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|
virtual void resume();
|
|
|
|
};
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|
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class IGbEInt : public EtherInt
|
|
{
|
|
private:
|
|
IGbE *dev;
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|
|
public:
|
|
IGbEInt(const std::string &name, IGbE *d)
|
|
: EtherInt(name), dev(d)
|
|
{ dev->setEthInt(this); }
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|
|
|
virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
|
|
virtual void sendDone() { dev->ethTxDone(); }
|
|
};
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#endif //__DEV_I8254XGBE_HH__
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