abc76f20cb
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
610 lines
16 KiB
C++
610 lines
16 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/locked_mem.hh"
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#include "arch/mmaped_ipr.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/simple/atomic.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/AtomicSimpleCPU.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
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{
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}
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void
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AtomicSimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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AtomicSimpleCPU::TickEvent::description()
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{
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return "AtomicSimpleCPU tick event";
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}
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Port *
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AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "dcache_port")
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return &dcachePort;
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else if (if_name == "icache_port")
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return &icachePort;
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else
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panic("No Such Port\n");
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}
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void
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AtomicSimpleCPU::init()
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{
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BaseCPU::init();
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#if FULL_SYSTEM
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(tc, tc->readCpuId());
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}
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#endif
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}
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bool
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AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
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{
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panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
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return true;
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}
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Tick
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AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
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{
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//Snooping a coherence request, just return
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return 0;
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}
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void
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AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
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{
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//No internal storage to update, just return
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return;
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}
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void
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AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
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}
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void
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AtomicSimpleCPU::CpuPort::recvRetry()
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{
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panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
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}
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void
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AtomicSimpleCPU::DcachePort::setPeer(Port *port)
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{
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Port::setPeer(port);
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#if FULL_SYSTEM
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// Update the ThreadContext's memory ports (Functional/Virtual
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// Ports)
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cpu->tcBase()->connectMemPorts();
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#endif
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}
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AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
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: BaseSimpleCPU(p), tickEvent(this),
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width(p->width), simulate_stalls(p->simulate_stalls),
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icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
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{
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_status = Idle;
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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ifetch_req = new Request();
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ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
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ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
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ifetch_pkt->dataStatic(&inst);
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data_read_req = new Request();
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data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
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Packet::Broadcast);
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data_read_pkt->dataStatic(&dataReg);
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data_write_req = new Request();
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data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
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data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
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Packet::Broadcast);
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data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
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Packet::Broadcast);
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}
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AtomicSimpleCPU::~AtomicSimpleCPU()
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{
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}
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void
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AtomicSimpleCPU::serialize(ostream &os)
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{
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SimObject::State so_state = SimObject::getState();
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SERIALIZE_ENUM(so_state);
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Status _status = status();
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SERIALIZE_ENUM(_status);
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BaseSimpleCPU::serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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}
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void
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AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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SimObject::State so_state;
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UNSERIALIZE_ENUM(so_state);
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UNSERIALIZE_ENUM(_status);
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BaseSimpleCPU::unserialize(cp, section);
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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}
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void
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AtomicSimpleCPU::resume()
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{
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if (_status != SwitchedOut && _status != Idle) {
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assert(system->getMemoryMode() == Enums::atomic);
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changeState(SimObject::Running);
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if (thread->status() == ThreadContext::Active) {
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if (!tickEvent.scheduled()) {
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tickEvent.schedule(nextCycle());
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}
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}
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}
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}
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void
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AtomicSimpleCPU::switchOut()
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{
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assert(status() == Running || status() == Idle);
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_status = SwitchedOut;
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tickEvent.squash();
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}
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void
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AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(nextCycle());
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break;
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}
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}
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if (_status != Running) {
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_status = Idle;
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}
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}
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void
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AtomicSimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(thread);
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assert(_status == Idle);
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assert(!tickEvent.scheduled());
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notIdleFraction++;
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//Make sure ticks are still on multiples of cycles
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tickEvent.schedule(nextCycle(curTick + cycles(delay)));
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_status = Running;
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}
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void
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AtomicSimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(thread);
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assert(_status == Running);
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// tick event may not be scheduled if this gets called from inside
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// an instruction's execution, e.g. "quiesce"
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if (tickEvent.scheduled())
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tickEvent.deschedule();
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notIdleFraction--;
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_status = Idle;
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}
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template <class T>
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Fault
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AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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// use the CPU's statically allocated read request and packet objects
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Request *req = data_read_req;
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PacketPtr pkt = data_read_pkt;
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req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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if (traceData) {
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traceData->setAddr(addr);
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}
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// translate to physical address
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Fault fault = thread->translateDataReadReq(req);
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// Now do the access.
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if (fault == NoFault) {
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pkt->reinitFromRequest();
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if (req->isMmapedIpr())
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dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
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else
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dcache_latency = dcachePort.sendAtomic(pkt);
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dcache_access = true;
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#if !defined(NDEBUG)
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if (pkt->result != Packet::Success)
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panic("Unable to find responder for address pa = %#X va = %#X\n",
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pkt->req->getPaddr(), pkt->req->getVaddr());
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#endif
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data = pkt->get<T>();
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if (req->isLocked()) {
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TheISA::handleLockedRead(thread, req);
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}
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}
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// This will need a new way to tell if it has a dcache attached.
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if (req->isUncacheable())
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recordEvent("Uncached Read");
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
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template
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Fault
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AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
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{
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return read(addr, *(uint64_t*)&data, flags);
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}
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template<>
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Fault
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AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
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{
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return read(addr, *(uint32_t*)&data, flags);
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}
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template<>
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Fault
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AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
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{
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return read(addr, (uint32_t&)data, flags);
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}
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template <class T>
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Fault
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AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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{
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// use the CPU's statically allocated write request and packet objects
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Request *req = data_write_req;
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PacketPtr pkt;
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req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
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if (req->isSwap())
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pkt = data_swap_pkt;
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else
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pkt = data_write_pkt;
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if (traceData) {
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traceData->setAddr(addr);
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}
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// translate to physical address
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Fault fault = thread->translateDataWriteReq(req);
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// Now do the access.
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if (fault == NoFault) {
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bool do_access = true; // flag to suppress cache access
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if (req->isLocked()) {
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do_access = TheISA::handleLockedWrite(thread, req);
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}
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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if (do_access) {
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pkt->reinitFromRequest();
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pkt->dataStatic(&data);
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if (req->isMmapedIpr()) {
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dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
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} else {
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data = htog(data);
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dcache_latency = dcachePort.sendAtomic(pkt);
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}
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dcache_access = true;
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#if !defined(NDEBUG)
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if (pkt->result != Packet::Success)
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panic("Unable to find responder for address pa = %#X va = %#X\n",
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pkt->req->getPaddr(), pkt->req->getVaddr());
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#endif
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}
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if (req->isSwap()) {
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assert(res);
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*res = pkt->get<T>();
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} else if (res) {
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*res = req->getExtraData();
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}
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}
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// This will need a new way to tell if it's hooked up to a cache or not.
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if (req->isUncacheable())
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recordEvent("Uncached Write");
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// If the write needs to have a fault on the access, consider calling
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// changeStatus() and changing it to "bad addr write" or something.
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return fault;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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template
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Fault
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AtomicSimpleCPU::write(Twin32_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(Twin64_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint64_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint32_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint16_t data, Addr addr,
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unsigned flags, uint64_t *res);
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template
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Fault
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AtomicSimpleCPU::write(uint8_t data, Addr addr,
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unsigned flags, uint64_t *res);
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#endif //DOXYGEN_SHOULD_SKIP_THIS
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template<>
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Fault
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AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint64_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write(*(uint32_t*)&data, addr, flags, res);
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}
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template<>
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Fault
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AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
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{
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return write((uint32_t)data, addr, flags, res);
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}
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void
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AtomicSimpleCPU::tick()
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{
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Tick latency = cycles(1); // instruction takes one cycle by default
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for (int i = 0; i < width; ++i) {
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numCycles++;
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if (!curStaticInst || !curStaticInst->isDelayedCommit())
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checkForInterrupts();
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Fault fault = setupFetchRequest(ifetch_req);
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if (fault == NoFault) {
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Tick icache_latency = 0;
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bool icache_access = false;
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dcache_access = false; // assume no dcache access
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//Fetch more instruction memory if necessary
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//if(predecoder.needMoreBytes())
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//{
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icache_access = true;
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ifetch_pkt->reinitFromRequest();
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icache_latency = icachePort.sendAtomic(ifetch_pkt);
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// ifetch_req is initialized to read the instruction directly
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// into the CPU object's inst field.
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//}
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preExecute();
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if(curStaticInst)
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{
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fault = curStaticInst->execute(this, traceData);
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postExecute();
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}
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// @todo remove me after debugging with legion done
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if (curStaticInst && (!curStaticInst->isMicroop() ||
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curStaticInst->isFirstMicroop()))
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instCnt++;
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if (simulate_stalls) {
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Tick icache_stall =
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icache_access ? icache_latency - cycles(1) : 0;
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Tick dcache_stall =
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dcache_access ? dcache_latency - cycles(1) : 0;
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Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
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if (cycles(stall_cycles) < (icache_stall + dcache_stall))
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latency += cycles(stall_cycles+1);
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else
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latency += cycles(stall_cycles);
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}
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}
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if(fault != NoFault || !stayAtPC)
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advancePC(fault);
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}
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if (_status != Idle)
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tickEvent.schedule(curTick + latency);
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}
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////////////////////////////////////////////////////////////////////////
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//
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// AtomicSimpleCPU Simulation Object
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//
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AtomicSimpleCPU *
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AtomicSimpleCPUParams::create()
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{
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AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
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params->name = name;
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params->numberOfThreads = 1;
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params->max_insts_any_thread = max_insts_any_thread;
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params->max_insts_all_threads = max_insts_all_threads;
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params->max_loads_any_thread = max_loads_any_thread;
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params->max_loads_all_threads = max_loads_all_threads;
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params->progress_interval = progress_interval;
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params->deferRegistration = defer_registration;
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params->phase = phase;
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params->clock = clock;
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params->functionTrace = function_trace;
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params->functionTraceStart = function_trace_start;
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params->width = width;
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params->simulate_stalls = simulate_stalls;
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params->system = system;
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params->cpu_id = cpu_id;
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#if FULL_SYSTEM
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params->itb = itb;
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params->dtb = dtb;
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params->profile = profile;
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params->do_quiesce = do_quiesce;
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params->do_checkpoint_insts = do_checkpoint_insts;
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params->do_statistics_insts = do_statistics_insts;
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#else
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if (workload.size() != 1)
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panic("only one workload allowed");
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params->process = workload[0];
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#endif
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AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
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return cpu;
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}
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