ab9c20cc78
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
32 lines
1.4 KiB
Plaintext
Executable file
32 lines
1.4 KiB
Plaintext
Executable file
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Feb 18 2011 15:40:30
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M5 revision Unknown
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M5 started Feb 18 2011 19:04:15
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M5 executing on m55-001.pool
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
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Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
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Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
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Standard Cell Placement and Global Routing Program
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Authors: Carl Sechen, Bill Swartz
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Yale University
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
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46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
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61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
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76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
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91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
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106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
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122 123 124 Exiting @ tick 40531279000 because target called exit()
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