464 lines
14 KiB
C++
464 lines
14 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/intmath.hh"
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#include "debug/RubyCache.hh"
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#include "mem/ruby/system/CacheMemory.hh"
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using namespace std;
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ostream&
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operator<<(ostream& out, const CacheMemory& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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CacheMemory *
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RubyCacheParams::create()
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{
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return new CacheMemory(this);
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}
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CacheMemory::CacheMemory(const Params *p)
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: SimObject(p)
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{
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m_cache_size = p->size;
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m_latency = p->latency;
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m_cache_assoc = p->assoc;
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m_policy = p->replacement_policy;
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m_profiler_ptr = new CacheProfiler(name());
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m_start_index_bit = p->start_index_bit;
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m_is_instruction_only_cache = p->is_icache;
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}
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void
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CacheMemory::init()
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{
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m_cache_num_sets = (m_cache_size / m_cache_assoc) /
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RubySystem::getBlockSizeBytes();
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assert(m_cache_num_sets > 1);
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m_cache_num_set_bits = floorLog2(m_cache_num_sets);
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assert(m_cache_num_set_bits > 0);
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if (m_policy == "PSEUDO_LRU")
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m_replacementPolicy_ptr =
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new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
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else if (m_policy == "LRU")
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m_replacementPolicy_ptr =
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new LRUPolicy(m_cache_num_sets, m_cache_assoc);
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else
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assert(false);
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m_cache.resize(m_cache_num_sets);
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for (int i = 0; i < m_cache_num_sets; i++) {
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m_cache[i].resize(m_cache_assoc);
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for (int j = 0; j < m_cache_assoc; j++) {
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m_cache[i][j] = NULL;
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}
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}
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}
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CacheMemory::~CacheMemory()
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{
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if (m_replacementPolicy_ptr != NULL)
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delete m_replacementPolicy_ptr;
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delete m_profiler_ptr;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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delete m_cache[i][j];
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}
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}
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}
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void
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CacheMemory::printConfig(ostream& out)
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{
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int block_size = RubySystem::getBlockSizeBytes();
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out << "Cache config: " << m_cache_name << endl;
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out << " cache_associativity: " << m_cache_assoc << endl;
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out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl;
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const int cache_num_sets = 1 << m_cache_num_set_bits;
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out << " num_cache_sets: " << cache_num_sets << endl;
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out << " cache_set_size_bytes: " << cache_num_sets * block_size << endl;
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out << " cache_set_size_Kbytes: "
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<< double(cache_num_sets * block_size) / (1<<10) << endl;
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out << " cache_set_size_Mbytes: "
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<< double(cache_num_sets * block_size) / (1<<20) << endl;
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out << " cache_size_bytes: "
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<< cache_num_sets * block_size * m_cache_assoc << endl;
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out << " cache_size_Kbytes: "
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<< double(cache_num_sets * block_size * m_cache_assoc) / (1<<10)
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<< endl;
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out << " cache_size_Mbytes: "
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<< double(cache_num_sets * block_size * m_cache_assoc) / (1<<20)
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<< endl;
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}
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// convert a Address to its location in the cache
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Index
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CacheMemory::addressToCacheSet(const Address& address) const
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{
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assert(address == line_address(address));
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return address.bitSelect(m_start_index_bit,
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m_start_index_bit + m_cache_num_set_bits - 1);
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int
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CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const
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{
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assert(tag == line_address(tag));
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// search the set for the tags
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m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
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if (it != m_tag_index.end())
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if (m_cache[cacheSet][it->second]->m_Permission !=
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AccessPermission_NotPresent)
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return it->second;
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return -1; // Not found
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int
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CacheMemory::findTagInSetIgnorePermissions(Index cacheSet,
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const Address& tag) const
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{
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assert(tag == line_address(tag));
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// search the set for the tags
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m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag);
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if (it != m_tag_index.end())
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return it->second;
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return -1; // Not found
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}
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bool
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CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == line_address(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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// Do we even have a tag match?
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AbstractCacheEntry* entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->
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touch(cacheSet, loc, g_eventQueue_ptr->getTime());
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data_ptr = &(entry->getDataBlk());
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if (entry->m_Permission == AccessPermission_Read_Write) {
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return true;
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}
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if ((entry->m_Permission == AccessPermission_Read_Only) &&
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(type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
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return true;
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}
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// The line must not be accessible
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}
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data_ptr = NULL;
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return false;
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}
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bool
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CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == line_address(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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// Do we even have a tag match?
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AbstractCacheEntry* entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->
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touch(cacheSet, loc, g_eventQueue_ptr->getTime());
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data_ptr = &(entry->getDataBlk());
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return m_cache[cacheSet][loc]->m_Permission !=
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AccessPermission_NotPresent;
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}
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data_ptr = NULL;
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return false;
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}
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// tests to see if an address is present in the cache
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bool
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CacheMemory::isTagPresent(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc == -1) {
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// We didn't find the tag
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DPRINTF(RubyCache, "No tag match for address: %s\n", address);
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return false;
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}
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DPRINTF(RubyCache, "address: %s found\n", address);
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return true;
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}
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an unused line in the same cache "way"
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bool
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CacheMemory::cacheAvail(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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for (int i = 0; i < m_cache_assoc; i++) {
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AbstractCacheEntry* entry = m_cache[cacheSet][i];
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if (entry != NULL) {
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if (entry->m_Address == address ||
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entry->m_Permission == AccessPermission_NotPresent) {
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// Already in the cache or we found an empty entry
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return true;
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}
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} else {
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return true;
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}
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}
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return false;
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}
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AbstractCacheEntry*
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CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
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{
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assert(address == line_address(address));
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assert(!isTagPresent(address));
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assert(cacheAvail(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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// Find the first open slot
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Index cacheSet = addressToCacheSet(address);
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std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
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for (int i = 0; i < m_cache_assoc; i++) {
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if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
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set[i] = entry; // Init entry
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set[i]->m_Address = address;
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set[i]->m_Permission = AccessPermission_Invalid;
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DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
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address);
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set[i]->m_locked = -1;
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m_tag_index[address] = i;
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m_replacementPolicy_ptr->
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touch(cacheSet, i, g_eventQueue_ptr->getTime());
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return entry;
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}
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}
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panic("Allocate didn't find an available entry");
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}
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void
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CacheMemory::deallocate(const Address& address)
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{
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assert(address == line_address(address));
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assert(isTagPresent(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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delete m_cache[cacheSet][loc];
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m_cache[cacheSet][loc] = NULL;
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m_tag_index.erase(address);
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}
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}
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// Returns with the physical address of the conflicting cache line
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Address
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CacheMemory::cacheProbe(const Address& address) const
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{
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assert(address == line_address(address));
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assert(!cacheAvail(address));
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Index cacheSet = addressToCacheSet(address);
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return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
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m_Address;
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}
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// looks an address up in the cache
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AbstractCacheEntry*
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CacheMemory::lookup(const Address& address)
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc == -1) return NULL;
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return m_cache[cacheSet][loc];
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}
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// looks an address up in the cache
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const AbstractCacheEntry*
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CacheMemory::lookup(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc == -1) return NULL;
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return m_cache[cacheSet][loc];
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}
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// Sets the most recently used bit for a cache block
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void
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CacheMemory::setMRU(const Address& address)
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{
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Index cacheSet;
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cacheSet = addressToCacheSet(address);
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m_replacementPolicy_ptr->
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touch(cacheSet, findTagInSet(cacheSet, address),
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g_eventQueue_ptr->getTime());
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}
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void
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CacheMemory::profileMiss(const RubyRequest& msg)
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{
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m_profiler_ptr->addCacheStatSample(msg.getType(),
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msg.getAccessMode(),
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msg.getPrefetch());
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}
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void
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CacheMemory::profileGenericRequest(GenericRequestType requestType,
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RubyAccessMode accessType,
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PrefetchBit pfBit)
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{
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m_profiler_ptr->addGenericStatSample(requestType,
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accessType,
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pfBit);
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}
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void
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CacheMemory::recordCacheContents(CacheRecorder& tr) const
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{
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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AccessPermission perm = m_cache[i][j]->m_Permission;
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RubyRequestType request_type = RubyRequestType_NULL;
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if (perm == AccessPermission_Read_Only) {
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if (m_is_instruction_only_cache) {
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request_type = RubyRequestType_IFETCH;
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} else {
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request_type = RubyRequestType_LD;
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}
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} else if (perm == AccessPermission_Read_Write) {
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request_type = RubyRequestType_ST;
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}
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if (request_type != RubyRequestType_NULL) {
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#if 0
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tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
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Address(0), request_type,
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m_replacementPolicy_ptr->getLastAccess(i, j));
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#endif
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}
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}
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}
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}
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void
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CacheMemory::print(ostream& out) const
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{
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out << "Cache dump: " << m_cache_name << endl;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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if (m_cache[i][j] != NULL) {
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out << " Index: " << i
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<< " way: " << j
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<< " entry: " << *m_cache[i][j] << endl;
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} else {
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out << " Index: " << i
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<< " way: " << j
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<< " entry: NULL" << endl;
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}
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}
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}
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}
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void
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CacheMemory::printData(ostream& out) const
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{
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out << "printData() not supported" << endl;
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}
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void
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CacheMemory::clearStats() const
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{
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m_profiler_ptr->clearStats();
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}
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void
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CacheMemory::printStats(ostream& out) const
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{
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m_profiler_ptr->printStats(out);
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}
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void
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CacheMemory::setLocked(const Address& address, int context)
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{
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DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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m_cache[cacheSet][loc]->m_locked = context;
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}
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void
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CacheMemory::clearLocked(const Address& address)
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{
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DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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m_cache[cacheSet][loc]->m_locked = -1;
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}
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bool
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CacheMemory::isLocked(const Address& address, int context)
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
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address, m_cache[cacheSet][loc]->m_locked, context);
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return m_cache[cacheSet][loc]->m_locked == context;
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}
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