319 lines
7.9 KiB
C++
Executable file
319 lines
7.9 KiB
C++
Executable file
/*
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* Copyright (c) 2010-2012 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
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#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
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#include "arch/kernel_stats.hh"
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#include "arch/registers.hh"
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#include "config/the_isa.hh"
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#include "cpu/o3/thread_context.hh"
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#include "cpu/quiesce_event.hh"
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#include "debug/O3CPU.hh"
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template <class Impl>
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FSTranslatingPortProxy&
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O3ThreadContext<Impl>::getVirtProxy()
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{
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return thread->getVirtProxy();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::dumpFuncProfile()
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{
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thread->dumpFuncProfile();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
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{
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::takeOverFrom(*this, *old_context);
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TheISA::Decoder *newDecoder = getDecoderPtr();
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TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
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newDecoder->takeOverFrom(oldDecoder);
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thread->kernelStats = old_context->getKernelStats();
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thread->funcExeInst = old_context->readFuncExeInst();
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thread->noSquashFromTC = false;
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thread->trapPending = false;
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::activate()
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{
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DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
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threadId());
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if (thread->status() == ThreadContext::Active)
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return;
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thread->lastActivate = curTick();
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thread->setStatus(ThreadContext::Active);
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// status() == Suspended
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cpu->activateContext(thread->threadId());
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::suspend()
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{
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DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
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threadId());
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if (thread->status() == ThreadContext::Suspended)
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return;
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thread->lastActivate = curTick();
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thread->lastSuspend = curTick();
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thread->setStatus(ThreadContext::Suspended);
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cpu->suspendContext(thread->threadId());
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::halt()
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{
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DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
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if (thread->status() == ThreadContext::Halted)
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return;
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thread->setStatus(ThreadContext::Halted);
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cpu->haltContext(thread->threadId());
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::regStats(const std::string &name)
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{
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if (FullSystem) {
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thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
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thread->kernelStats->regStats(name + ".kern");
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}
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}
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template <class Impl>
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Tick
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O3ThreadContext<Impl>::readLastActivate()
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{
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return thread->lastActivate;
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}
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template <class Impl>
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Tick
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O3ThreadContext<Impl>::readLastSuspend()
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{
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return thread->lastSuspend;
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::profileClear()
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{
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thread->profileClear();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::profileSample()
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{
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thread->profileSample();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
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{
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// Prevent squashing
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thread->noSquashFromTC = true;
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TheISA::copyRegs(tc, this);
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thread->noSquashFromTC = false;
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if (!FullSystem)
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this->thread->funcExeInst = tc->readFuncExeInst();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::clearArchRegs()
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{
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cpu->isa[thread->threadId()]->clear();
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}
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template <class Impl>
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uint64_t
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O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
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{
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return cpu->readArchIntReg(reg_idx, thread->threadId());
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}
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template <class Impl>
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TheISA::FloatReg
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O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
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{
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return cpu->readArchFloatReg(reg_idx, thread->threadId());
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}
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template <class Impl>
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TheISA::FloatRegBits
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O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
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{
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return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
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}
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template <class Impl>
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TheISA::CCReg
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O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
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{
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return cpu->readArchCCReg(reg_idx, thread->threadId());
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
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{
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cpu->setArchIntReg(reg_idx, val, thread->threadId());
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conditionalSquash();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
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{
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cpu->setArchFloatReg(reg_idx, val, thread->threadId());
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conditionalSquash();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
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{
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cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
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conditionalSquash();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
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{
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cpu->setArchCCReg(reg_idx, val, thread->threadId());
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conditionalSquash();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
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{
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cpu->pcState(val, thread->threadId());
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conditionalSquash();
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
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{
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cpu->pcState(val, thread->threadId());
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conditionalSquash();
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}
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template <class Impl>
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int
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O3ThreadContext<Impl>::flattenIntIndex(int reg)
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{
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return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
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}
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template <class Impl>
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int
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O3ThreadContext<Impl>::flattenFloatIndex(int reg)
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{
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return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
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}
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template <class Impl>
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int
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O3ThreadContext<Impl>::flattenCCIndex(int reg)
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{
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return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
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}
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template <class Impl>
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int
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O3ThreadContext<Impl>::flattenMiscIndex(int reg)
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{
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return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
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}
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template <class Impl>
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void
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O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
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conditionalSquash();
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}
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#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
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template <class Impl>
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void
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O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
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{
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cpu->setMiscReg(misc_reg, val, thread->threadId());
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conditionalSquash();
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}
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