337 lines
10 KiB
C++
337 lines
10 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
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#define __CPU_CHECKER_THREAD_CONTEXT_HH__
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#include "arch/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Checker.hh"
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class EndQuiesceEvent;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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};
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class Decoder;
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};
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/**
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* Derived ThreadContext class for use with the Checker. The template
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* parameter is the ThreadContext class used by the specific CPU being
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* verified. This CheckerThreadContext is then used by the main CPU
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* in place of its usual ThreadContext class. It handles updating the
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* checker's state any time state is updated externally through the
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* ThreadContext.
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*/
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template <class TC>
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class CheckerThreadContext : public ThreadContext
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{
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public:
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CheckerThreadContext(TC *actual_tc,
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CheckerCPU *checker_cpu)
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: actualTC(actual_tc), checkerTC(checker_cpu->thread),
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checkerCPU(checker_cpu)
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{ }
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private:
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/** The main CPU's ThreadContext, or class that implements the
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* ThreadContext interface. */
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TC *actualTC;
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/** The checker's own SimpleThread. Will be updated any time
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* anything uses this ThreadContext to externally update a
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* thread's state. */
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SimpleThread *checkerTC;
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/** Pointer to the checker CPU. */
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CheckerCPU *checkerCPU;
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public:
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BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
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uint32_t socketId() const { return actualTC->socketId(); }
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int cpuId() const { return actualTC->cpuId(); }
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int contextId() const { return actualTC->contextId(); }
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void setContextId(int id)
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{
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actualTC->setContextId(id);
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checkerTC->setContextId(id);
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}
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/** Returns this thread's ID number. */
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int threadId() const { return actualTC->threadId(); }
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void setThreadId(int id)
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{
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checkerTC->setThreadId(id);
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actualTC->setThreadId(id);
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}
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TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
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TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
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CheckerCPU *getCheckerCpuPtr()
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{
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return checkerCPU;
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}
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TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
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System *getSystemPtr() { return actualTC->getSystemPtr(); }
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TheISA::Kernel::Statistics *getKernelStats()
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{ return actualTC->getKernelStats(); }
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Process *getProcessPtr() { return actualTC->getProcessPtr(); }
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PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); }
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FSTranslatingPortProxy &getVirtProxy()
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{ return actualTC->getVirtProxy(); }
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void initMemProxies(ThreadContext *tc)
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{ actualTC->initMemProxies(tc); }
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void connectMemPorts(ThreadContext *tc)
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{
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actualTC->connectMemPorts(tc);
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}
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SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); }
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/** Executes a syscall in SE mode. */
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void syscall(int64_t callnum)
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{ return actualTC->syscall(callnum); }
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Status status() const { return actualTC->status(); }
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void setStatus(Status new_status)
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{
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actualTC->setStatus(new_status);
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checkerTC->setStatus(new_status);
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}
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/// Set the status to Active.
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void activate() { actualTC->activate(); }
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/// Set the status to Suspended.
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void suspend() { actualTC->suspend(); }
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/// Set the status to Halted.
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void halt() { actualTC->halt(); }
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void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
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void takeOverFrom(ThreadContext *oldContext)
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{
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actualTC->takeOverFrom(oldContext);
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checkerTC->copyState(oldContext);
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}
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void regStats(const std::string &name)
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{
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actualTC->regStats(name);
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checkerTC->regStats(name);
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}
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EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
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Tick readLastActivate() { return actualTC->readLastActivate(); }
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Tick readLastSuspend() { return actualTC->readLastSuspend(); }
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void profileClear() { return actualTC->profileClear(); }
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void profileSample() { return actualTC->profileSample(); }
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// @todo: Do I need this?
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void copyArchRegs(ThreadContext *tc)
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{
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actualTC->copyArchRegs(tc);
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checkerTC->copyArchRegs(tc);
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}
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void clearArchRegs()
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{
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actualTC->clearArchRegs();
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checkerTC->clearArchRegs();
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}
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{ return actualTC->readIntReg(reg_idx); }
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FloatReg readFloatReg(int reg_idx)
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{ return actualTC->readFloatReg(reg_idx); }
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FloatRegBits readFloatRegBits(int reg_idx)
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{ return actualTC->readFloatRegBits(reg_idx); }
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CCReg readCCReg(int reg_idx)
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{ return actualTC->readCCReg(reg_idx); }
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void setIntReg(int reg_idx, uint64_t val)
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{
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actualTC->setIntReg(reg_idx, val);
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checkerTC->setIntReg(reg_idx, val);
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}
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void setFloatReg(int reg_idx, FloatReg val)
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{
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actualTC->setFloatReg(reg_idx, val);
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checkerTC->setFloatReg(reg_idx, val);
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}
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{
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actualTC->setFloatRegBits(reg_idx, val);
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checkerTC->setFloatRegBits(reg_idx, val);
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}
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void setCCReg(int reg_idx, CCReg val)
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{
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actualTC->setCCReg(reg_idx, val);
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checkerTC->setCCReg(reg_idx, val);
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}
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/** Reads this thread's PC state. */
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TheISA::PCState pcState()
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{ return actualTC->pcState(); }
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/** Sets this thread's PC state. */
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void pcState(const TheISA::PCState &val)
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{
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DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
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val, checkerTC->pcState());
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checkerTC->pcState(val);
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checkerCPU->recordPCChange(val);
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return actualTC->pcState(val);
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}
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void pcStateNoRecord(const TheISA::PCState &val)
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{
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return actualTC->pcState(val);
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}
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/** Reads this thread's PC. */
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Addr instAddr()
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{ return actualTC->instAddr(); }
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/** Reads this thread's next PC. */
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Addr nextInstAddr()
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{ return actualTC->nextInstAddr(); }
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/** Reads this thread's next PC. */
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MicroPC microPC()
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{ return actualTC->microPC(); }
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MiscReg readMiscRegNoEffect(int misc_reg) const
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{ return actualTC->readMiscRegNoEffect(misc_reg); }
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MiscReg readMiscReg(int misc_reg)
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{ return actualTC->readMiscReg(misc_reg); }
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
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" and O3..\n", misc_reg);
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checkerTC->setMiscRegNoEffect(misc_reg, val);
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actualTC->setMiscRegNoEffect(misc_reg, val);
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}
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void setMiscReg(int misc_reg, const MiscReg &val)
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{
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DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
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" and O3..\n", misc_reg);
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checkerTC->setMiscReg(misc_reg, val);
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actualTC->setMiscReg(misc_reg, val);
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}
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int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
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int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
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int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
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int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
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unsigned readStCondFailures()
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{ return actualTC->readStCondFailures(); }
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void setStCondFailures(unsigned sc_failures)
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{
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actualTC->setStCondFailures(sc_failures);
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}
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Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
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uint64_t readIntRegFlat(int idx)
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{ return actualTC->readIntRegFlat(idx); }
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void setIntRegFlat(int idx, uint64_t val)
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{ actualTC->setIntRegFlat(idx, val); }
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FloatReg readFloatRegFlat(int idx)
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{ return actualTC->readFloatRegFlat(idx); }
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void setFloatRegFlat(int idx, FloatReg val)
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{ actualTC->setFloatRegFlat(idx, val); }
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FloatRegBits readFloatRegBitsFlat(int idx)
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{ return actualTC->readFloatRegBitsFlat(idx); }
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void setFloatRegBitsFlat(int idx, FloatRegBits val)
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{ actualTC->setFloatRegBitsFlat(idx, val); }
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CCReg readCCRegFlat(int idx)
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{ return actualTC->readCCRegFlat(idx); }
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void setCCRegFlat(int idx, CCReg val)
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{ actualTC->setCCRegFlat(idx, val); }
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};
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#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
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