6629d9b2bc
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. |
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| .. | ||
| Benchmarks.py | ||
| Caches.py | ||
| cpu2000.py | ||
| FSConfig.py | ||
| Options.py | ||
| Simulation.py | ||
| SysPaths.py | ||