Doxyfile: Turn on EXTRACT_ALL so we get full class hierarchy info. base/range.hh: cpu/o3/fetch.hh: cpu/o3/rename_map.hh: cpu/o3/rob.hh: dev/ide_disk.cc: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.hh: Fix doxygen issues. --HG-- extra : convert_revision : 9e0e8d3510b35db201459b8a3211c5e6ad5f0bb4
174 lines
5.4 KiB
C++
174 lines
5.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Emulation of the Tsunami CChip CSRs
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*/
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#ifndef __TSUNAMI_CCHIP_HH__
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#define __TSUNAMI_CCHIP_HH__
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#include "dev/tsunami.hh"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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/**
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* Tsunami CChip CSR Emulation. This device includes all the interrupt
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* handling code for the chipset.
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*/
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class TsunamiCChip : public PioDevice
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{
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private:
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/** The base address of this device */
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Addr addr;
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/** The size of mappad from the above address */
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static const Addr size = 0xfffffff;
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protected:
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/**
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* pointer to the tsunami object.
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* This is our access to all the other tsunami
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* devices.
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*/
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Tsunami *tsunami;
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/**
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* The dims are device interrupt mask registers.
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* One exists for each CPU, the DRIR X DIM = DIR
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*/
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uint64_t dim[Tsunami::Max_CPUs];
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/**
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* The dirs are device interrupt registers.
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* One exists for each CPU, the DRIR X DIM = DIR
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*/
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uint64_t dir[Tsunami::Max_CPUs];
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/**
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* This register contains bits for each PCI interrupt
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* that can occur.
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*/
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uint64_t drir;
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/** Indicator of which CPUs have an IPI interrupt */
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uint64_t ipint;
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/** Indicator of which CPUs have an RTC interrupt */
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uint64_t itint;
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public:
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/**
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* Initialize the Tsunami CChip by setting all of the
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* device register to 0.
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* @param name name of this device.
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* @param t pointer back to the Tsunami object that we belong to.
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* @param a address we are mapped at.
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* @param mmu pointer to the memory controller that sends us events.
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* @param hier object to store parameters universal the device hierarchy
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* @param bus The bus that this device is attached to
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*/
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TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
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MemoryController *mmu, HierParams *hier, Bus *bus,
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Tick pio_latency);
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/**
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* Process a read to the CChip.
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* @param req Contains the address to read from.
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* @param data A pointer to write the read data to.
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* @return The fault condition of the access.
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*/
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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/**
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* Process a write to the CChip.
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* @param req Contains the address to write to.
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* @param data The data to write.
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* @return The fault condition of the access.
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*/
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* post an RTC interrupt to the CPU
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*/
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void postRTC();
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/**
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* post an interrupt to the CPU.
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* @param interrupt the interrupt number to post (0-64)
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*/
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void postDRIR(uint32_t interrupt);
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/**
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* clear an interrupt previously posted to the CPU.
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* @param interrupt the interrupt number to post (0-64)
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*/
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void clearDRIR(uint32_t interrupt);
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/**
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* post an ipi interrupt to the CPU.
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* @param ipintr the cpu number to clear(bitvector)
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*/
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void clearIPI(uint64_t ipintr);
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/**
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* clear a timer interrupt previously posted to the CPU.
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* @param itintr the cpu number to clear(bitvector)
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*/
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void clearITI(uint64_t itintr);
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/**
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* request an interrupt be posted to the CPU.
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* @param ipreq the cpu number to interrupt(bitvector)
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*/
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void reqIPI(uint64_t ipreq);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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virtual void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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/**
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* Return how long this access will take.
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* @param req the memory request to calcuate
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* @return Tick when the request is done
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*/
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Tick cacheAccess(MemReqPtr &req);
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};
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#endif // __TSUNAMI_CCHIP_HH__
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