gem5/dev/pciconfigall.cc
Steve Reinhardt ad8b9636f8 Many files:
Update copyright dates and author list

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
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arch/alpha/pseudo_inst.cc:
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base/bitfield.hh:
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base/fast_alloc.cc:
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base/fifo_buffer.cc:
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base/hashmap.hh:
base/hostinfo.cc:
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base/hybrid_pred.cc:
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base/loader/aout_object.cc:
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base/loader/elf_object.cc:
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base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
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docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
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kern/tru64/printf.cc:
kern/tru64/printf.hh:
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kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
    Update copyright dates and author list

--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 05:16:00 -04:00

245 lines
7.7 KiB
C++

/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* @file
* PCI Configspace implementation
*/
#include <deque>
#include <string>
#include <vector>
#include <bitset>
#include "base/trace.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
#include "dev/pcireg.h"
#include "mem/bus/bus.hh"
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
PciConfigAll::PciConfigAll(const string &name,
Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, Tick pio_latency)
: PioDevice(name, NULL), addr(a)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
&PciConfigAll::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
}
// Make all the pointers to devices null
for(int x=0; x < MAX_PCI_DEV; x++)
for(int y=0; y < MAX_PCI_FUNC; y++)
devices[x][y] = NULL;
}
// If two interrupts share the same line largely bad things will happen.
// Since we don't track how many times an interrupt was set and correspondingly
// cleared two devices on the same interrupt line and assert and deassert each
// others interrupt "line". Interrupts will not work correctly.
void
PciConfigAll::startup()
{
bitset<256> intLines;
PciDev *tempDev;
uint8_t intline;
for (int x = 0; x < MAX_PCI_DEV; x++) {
for (int y = 0; y < MAX_PCI_FUNC; y++) {
if (devices[x][y] != NULL) {
tempDev = devices[x][y];
intline = tempDev->interruptLine();
if (intLines.test(intline))
warn("Interrupt line %#X is used multiple times"
"(You probably want to fix this).\n", (uint32_t)intline);
else
intLines.set(intline);
} // devices != NULL
} // PCI_FUNC
} // PCI_DEV
}
Fault
PciConfigAll::read(MemReqPtr &req, uint8_t *data)
{
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n",
req->vaddr, daddr, req->size);
int device = (daddr >> 11) & 0x1F;
int func = (daddr >> 8) & 0x7;
int reg = daddr & 0xFF;
if (devices[device][func] == NULL) {
switch (req->size) {
// case sizeof(uint64_t):
// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
// return No_Fault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
return No_Fault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
return No_Fault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
return No_Fault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
} else {
switch (req->size) {
case sizeof(uint32_t):
case sizeof(uint16_t):
case sizeof(uint8_t):
devices[device][func]->ReadConfig(reg, req->size, data);
return No_Fault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
}
DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
daddr, req->size);
return No_Fault;
}
Fault
PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
int device = (daddr >> 11) & 0x1F;
int func = (daddr >> 8) & 0x7;
int reg = daddr & 0xFF;
union {
uint8_t byte_value;
uint16_t half_value;
uint32_t word_value;
};
if (devices[device][func] == NULL)
panic("Attempting to write to config space on non-existant device\n");
else {
switch (req->size) {
case sizeof(uint8_t):
byte_value = *(uint8_t*)data;
break;
case sizeof(uint16_t):
half_value = *(uint16_t*)data;
break;
case sizeof(uint32_t):
word_value = *(uint32_t*)data;
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
}
DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
req->vaddr, req->size, word_value);
devices[device][func]->WriteConfig(reg, req->size, word_value);
return No_Fault;
}
void
PciConfigAll::serialize(std::ostream &os)
{
/*
* There is no state associated with this object that requires
* serialization. The only real state are the device pointers
* which are all setup by the constructor of the PciDev class
*/
}
void
PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
{
/*
* There is no state associated with this object that requires
* serialization. The only real state are the device pointers
* which are all setup by the constructor of the PciDev class
*/
}
Tick
PciConfigAll::cacheAccess(MemReqPtr &req)
{
return curTick + pioLatency;
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
SimObjectParam<Bus*> io_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
{
return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
pio_latency);
}
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
#endif // DOXYGEN_SHOULD_SKIP_THIS