Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
361 lines
9.4 KiB
C++
361 lines
9.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Device model for an IDE disk
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*/
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#ifndef __IDE_DISK_HH__
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#define __IDE_DISK_HH__
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#include "dev/disk_image.hh"
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#include "dev/ide_atareg.h"
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#include "dev/ide_wdcreg.h"
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#include "dev/io_device.hh"
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#include "sim/eventq.hh"
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#define DMA_BACKOFF_PERIOD 200
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#define MAX_DMA_SIZE (65536) // 64K
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#define MAX_MULTSECT (128)
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#define PRD_BASE_MASK 0xfffffffe
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#define PRD_COUNT_MASK 0xfffe
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#define PRD_EOT_MASK 0x8000
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typedef struct PrdEntry {
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uint32_t baseAddr;
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uint16_t byteCount;
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uint16_t endOfTable;
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} PrdEntry_t;
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class PrdTableEntry {
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public:
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PrdEntry_t entry;
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uint32_t getBaseAddr()
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{
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return (entry.baseAddr & PRD_BASE_MASK);
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}
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uint32_t getByteCount()
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{
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return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
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(entry.byteCount & PRD_COUNT_MASK));
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}
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uint16_t getEOT()
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{
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return (entry.endOfTable & PRD_EOT_MASK);
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}
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};
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#define DATA_OFFSET (0)
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#define ERROR_OFFSET (1)
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#define FEATURES_OFFSET (1)
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#define NSECTOR_OFFSET (2)
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#define SECTOR_OFFSET (3)
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#define LCYL_OFFSET (4)
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#define HCYL_OFFSET (5)
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#define SELECT_OFFSET (6)
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#define STATUS_OFFSET (7)
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#define COMMAND_OFFSET (7)
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#define CONTROL_OFFSET (2)
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#define ALTSTAT_OFFSET (2)
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#define SELECT_DEV_BIT 0x10
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#define CONTROL_RST_BIT 0x04
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#define CONTROL_IEN_BIT 0x02
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#define STATUS_BSY_BIT 0x80
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#define STATUS_DRDY_BIT 0x40
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#define STATUS_DRQ_BIT 0x08
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#define STATUS_SEEK_BIT 0x10
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#define STATUS_DF_BIT 0x20
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#define DRIVE_LBA_BIT 0x40
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#define DEV0 (0)
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#define DEV1 (1)
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typedef struct CommandReg {
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uint8_t data0;
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union {
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uint8_t data1;
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uint8_t error;
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uint8_t features;
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};
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uint8_t sec_count;
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uint8_t sec_num;
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uint8_t cyl_low;
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uint8_t cyl_high;
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union {
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uint8_t drive;
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uint8_t head;
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};
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uint8_t command;
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} CommandReg_t;
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typedef enum Events {
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None = 0,
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Transfer,
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ReadWait,
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WriteWait,
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PrdRead,
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DmaRead,
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DmaWrite
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} Events_t;
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typedef enum DevAction {
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ACT_NONE = 0,
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ACT_CMD_WRITE,
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ACT_CMD_COMPLETE,
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ACT_CMD_ERROR,
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ACT_SELECT_WRITE,
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ACT_STAT_READ,
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ACT_DATA_READY,
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ACT_DATA_READ_BYTE,
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ACT_DATA_READ_SHORT,
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ACT_DATA_WRITE_BYTE,
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ACT_DATA_WRITE_SHORT,
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ACT_DMA_READY,
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ACT_DMA_DONE,
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ACT_SRST_SET,
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ACT_SRST_CLEAR
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} DevAction_t;
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typedef enum DevState {
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// Device idle
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Device_Idle_S = 0,
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Device_Idle_SI,
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Device_Idle_NS,
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// Software reset
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Device_Srst,
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// Non-data commands
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Command_Execution,
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// PIO data-in (data to host)
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Prepare_Data_In,
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Data_Ready_INTRQ_In,
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Transfer_Data_In,
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// PIO data-out (data from host)
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Prepare_Data_Out,
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Data_Ready_INTRQ_Out,
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Transfer_Data_Out,
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// DMA protocol
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Prepare_Data_Dma,
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Transfer_Data_Dma
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} DevState_t;
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typedef enum DmaState {
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Dma_Idle = 0,
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Dma_Start,
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Dma_Transfer
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} DmaState_t;
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class PhysicalMemory;
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class IdeController;
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/**
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* IDE Disk device model
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*/
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class IdeDisk : public SimObject
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{
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protected:
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/** The IDE controller for this disk. */
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IdeController *ctrl;
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/** The DMA interface to use for transfers */
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DMAInterface<Bus> *dmaInterface;
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/** The image that contains the data of this disk. */
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DiskImage *image;
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/** Pointer to physical memory for DMA transfers */
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PhysicalMemory *physmem;
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protected:
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/** The disk delay in microseconds. */
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int diskDelay;
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private:
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/** Drive identification structure for this disk */
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struct ataparams driveID;
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/** Data buffer for transfers */
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uint8_t *dataBuffer;
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/** Number of bytes in command data transfer */
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uint32_t cmdBytes;
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/** Number of bytes left in command data transfer */
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uint32_t cmdBytesLeft;
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/** Number of bytes left in DRQ block */
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uint32_t drqBytesLeft;
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/** Current sector in access */
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uint32_t curSector;
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/** Command block registers */
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CommandReg_t cmdReg;
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/** Status register */
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uint8_t status;
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/** Interrupt enable bit */
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bool nIENBit;
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/** Device state */
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DevState_t devState;
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/** Dma state */
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DmaState_t dmaState;
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/** Dma transaction is a read */
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bool dmaRead;
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/** PRD table base address */
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uint32_t curPrdAddr;
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/** PRD entry */
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PrdTableEntry curPrd;
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/** Number of bytes transfered by DMA interface for current transfer */
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uint32_t dmaInterfaceBytes;
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/** Device ID (master=0/slave=1) */
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int devID;
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/** Interrupt pending */
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bool intrPending;
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public:
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/**
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* Create and initialize this Disk.
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* @param name The name of this disk.
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* @param img The disk image of this disk.
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* @param phys Pointer to physical memory
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* @param id The disk ID (master=0/slave=1)
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* @param disk_delay The disk delay in milliseconds
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*/
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IdeDisk(const std::string &name, DiskImage *img, PhysicalMemory *phys,
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int id, Tick disk_delay);
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/**
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* Delete the data buffer.
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*/
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~IdeDisk();
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/**
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* Reset the device state
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*/
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void reset(int id);
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/**
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* Set the controller for this device
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* @param c The IDE controller
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*/
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void setController(IdeController *c, DMAInterface<Bus> *dmaIntr) {
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if (ctrl) panic("Cannot change the controller once set!\n");
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ctrl = c;
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dmaInterface = dmaIntr;
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}
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// Device register read/write
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void read(const Addr &offset, bool byte, bool cmdBlk, uint8_t *data);
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void write(const Addr &offset, bool byte, bool cmdBlk, const uint8_t *data);
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// Start/abort functions
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void startDma(const uint32_t &prdTableBase);
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void abortDma();
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private:
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void startCommand();
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// Interrupt management
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void intrPost();
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void intrClear();
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// DMA stuff
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void doDmaTransfer();
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friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
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EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
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void doDmaRead();
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friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
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EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
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void doDmaWrite();
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friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
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EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
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void dmaPrdReadDone();
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friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
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EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
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void dmaReadDone();
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friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
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EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
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void dmaWriteDone();
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friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
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EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
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// Disk image read/write
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void readDisk(uint32_t sector, uint8_t *data);
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void writeDisk(uint32_t sector, uint8_t *data);
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// State machine management
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void updateState(DevAction_t action);
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// Utility functions
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bool isBSYSet() { return (status & STATUS_BSY_BIT); }
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bool isIENSet() { return nIENBit; }
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bool isDEVSelect();
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void setComplete()
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{
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// clear out the status byte
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status = 0;
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// set the DRDY bit
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status |= STATUS_DRDY_BIT;
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// set the SEEK bit
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status |= STATUS_SEEK_BIT;
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}
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uint32_t getLBABase()
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{
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return (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
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(cmdReg.cyl_low << 8) | (cmdReg.sec_num));
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}
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inline Addr pciToDma(Addr pciAddr);
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uint32_t bytesInDmaPage(Addr curAddr, uint32_t bytesLeft);
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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*/
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void serialize(std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param cp The checkpoint to use.
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* @param section The section name describing this object.
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*/
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __IDE_DISK_HH__
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