Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
365 lines
12 KiB
C++
365 lines
12 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Alpha Console Definition
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*/
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#include <cstddef>
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#include <cstdio>
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#include <string>
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number()
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "dev/alpha_console.hh"
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#include "dev/simconsole.hh"
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#include "dev/simple_disk.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "mem/functional/physical.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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#include "dev/tsunami_io.hh"
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#include "sim/sim_object.hh"
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#include "targetarch/byte_swap.hh"
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using namespace std;
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
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System *s, BaseCPU *c, Platform *p,
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int num_cpus, MemoryController *mmu, Addr a,
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HierParams *hier, Bus *bus)
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: PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&AlphaConsole::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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}
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alphaAccess = new AlphaAccess;
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alphaAccess->last_offset = size - 1;
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alphaAccess->version = ALPHA_ACCESS_VERSION;
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alphaAccess->numCPUs = num_cpus;
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alphaAccess->diskUnit = 1;
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alphaAccess->diskCount = 0;
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alphaAccess->diskPAddr = 0;
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alphaAccess->diskBlock = 0;
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alphaAccess->diskOperation = 0;
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alphaAccess->outputChar = 0;
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alphaAccess->inputChar = 0;
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alphaAccess->bootStrapImpure = 0;
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alphaAccess->bootStrapCPU = 0;
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alphaAccess->align2 = 0;
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}
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void
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AlphaConsole::init()
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{
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alphaAccess->kernStart = system->getKernelStart();
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alphaAccess->kernEnd = system->getKernelEnd();
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alphaAccess->entryPoint = system->getKernelEntry();
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alphaAccess->mem_size = system->physmem->size();
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alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
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alphaAccess->intrClockFrequency = platform->intrFrequency();
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}
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Fault
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AlphaConsole::read(MemReqPtr &req, uint8_t *data)
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{
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memset(data, 0, req->size);
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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switch (req->size)
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{
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case sizeof(uint32_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint32_t*)data);
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switch (daddr)
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{
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case offsetof(AlphaAccess, last_offset):
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*(uint32_t*)data = alphaAccess->last_offset;
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break;
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case offsetof(AlphaAccess, version):
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*(uint32_t*)data = alphaAccess->version;
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break;
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case offsetof(AlphaAccess, numCPUs):
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*(uint32_t*)data = alphaAccess->numCPUs;
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break;
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case offsetof(AlphaAccess, bootStrapCPU):
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*(uint32_t*)data = alphaAccess->bootStrapCPU;
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break;
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case offsetof(AlphaAccess, intrClockFrequency):
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*(uint32_t*)data = alphaAccess->intrClockFrequency;
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break;
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default:
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// Old console code read in everyting as a 32bit int
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*(uint32_t*)data = *(uint32_t*)(consoleData + daddr);
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}
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break;
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case sizeof(uint64_t):
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *(uint64_t*)data);
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switch (daddr)
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{
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case offsetof(AlphaAccess, inputChar):
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*(uint64_t*)data = console->console_in();
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break;
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case offsetof(AlphaAccess, cpuClock):
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*(uint64_t*)data = alphaAccess->cpuClock;
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break;
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case offsetof(AlphaAccess, mem_size):
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*(uint64_t*)data = alphaAccess->mem_size;
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break;
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case offsetof(AlphaAccess, kernStart):
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*(uint64_t*)data = alphaAccess->kernStart;
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break;
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case offsetof(AlphaAccess, kernEnd):
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*(uint64_t*)data = alphaAccess->kernEnd;
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break;
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case offsetof(AlphaAccess, entryPoint):
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*(uint64_t*)data = alphaAccess->entryPoint;
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break;
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case offsetof(AlphaAccess, diskUnit):
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*(uint64_t*)data = alphaAccess->diskUnit;
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break;
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case offsetof(AlphaAccess, diskCount):
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*(uint64_t*)data = alphaAccess->diskCount;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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*(uint64_t*)data = alphaAccess->diskPAddr;
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break;
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case offsetof(AlphaAccess, diskBlock):
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*(uint64_t*)data = alphaAccess->diskBlock;
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break;
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case offsetof(AlphaAccess, diskOperation):
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*(uint64_t*)data = alphaAccess->diskOperation;
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break;
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case offsetof(AlphaAccess, outputChar):
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*(uint64_t*)data = alphaAccess->outputChar;
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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*(uint64_t*)data = alphaAccess->bootStrapImpure;
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break;
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default:
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panic("Unknown 64bit access, %#x\n", daddr);
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}
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break;
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default:
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return Machine_Check_Fault;
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}
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return No_Fault;
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}
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Fault
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AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
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{
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uint64_t val;
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switch (req->size) {
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case sizeof(uint32_t):
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val = *(uint32_t *)data;
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break;
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case sizeof(uint64_t):
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val = *(uint64_t *)data;
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break;
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default:
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return Machine_Check_Fault;
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}
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Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
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ExecContext *other_xc;
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switch (daddr) {
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case offsetof(AlphaAccess, diskUnit):
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alphaAccess->diskUnit = val;
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break;
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case offsetof(AlphaAccess, diskCount):
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alphaAccess->diskCount = val;
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break;
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case offsetof(AlphaAccess, diskPAddr):
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alphaAccess->diskPAddr = val;
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break;
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case offsetof(AlphaAccess, diskBlock):
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alphaAccess->diskBlock = val;
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break;
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case offsetof(AlphaAccess, diskOperation):
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if (val == 0x13)
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disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
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alphaAccess->diskCount);
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else
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panic("Invalid disk operation!");
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break;
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case offsetof(AlphaAccess, outputChar):
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console->out((char)(val & 0xff));
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break;
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case offsetof(AlphaAccess, bootStrapImpure):
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alphaAccess->bootStrapImpure = val;
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break;
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case offsetof(AlphaAccess, bootStrapCPU):
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warn("%d: Trying to launch another CPU!", curTick);
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assert(val > 0 && "Must not access primary cpu");
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other_xc = req->xc->system->execContexts[val];
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other_xc->regs.intRegFile[16] = val;
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other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
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other_xc->regs.intRegFile[0] = val;
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other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
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other_xc->activate(); //Start the cpu
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break;
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default:
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return Machine_Check_Fault;
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}
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return No_Fault;
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}
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Tick
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AlphaConsole::cacheAccess(MemReqPtr &req)
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{
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return curTick + 1000;
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}
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void
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AlphaAccess::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(last_offset);
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SERIALIZE_SCALAR(version);
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SERIALIZE_SCALAR(numCPUs);
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SERIALIZE_SCALAR(mem_size);
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SERIALIZE_SCALAR(cpuClock);
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SERIALIZE_SCALAR(intrClockFrequency);
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SERIALIZE_SCALAR(kernStart);
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SERIALIZE_SCALAR(kernEnd);
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SERIALIZE_SCALAR(entryPoint);
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SERIALIZE_SCALAR(diskUnit);
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SERIALIZE_SCALAR(diskCount);
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SERIALIZE_SCALAR(diskPAddr);
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SERIALIZE_SCALAR(diskBlock);
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SERIALIZE_SCALAR(diskOperation);
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SERIALIZE_SCALAR(outputChar);
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SERIALIZE_SCALAR(inputChar);
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SERIALIZE_SCALAR(bootStrapImpure);
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SERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaAccess::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(last_offset);
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UNSERIALIZE_SCALAR(version);
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UNSERIALIZE_SCALAR(numCPUs);
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UNSERIALIZE_SCALAR(mem_size);
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UNSERIALIZE_SCALAR(cpuClock);
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UNSERIALIZE_SCALAR(intrClockFrequency);
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UNSERIALIZE_SCALAR(kernStart);
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UNSERIALIZE_SCALAR(kernEnd);
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UNSERIALIZE_SCALAR(entryPoint);
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UNSERIALIZE_SCALAR(diskUnit);
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UNSERIALIZE_SCALAR(diskCount);
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UNSERIALIZE_SCALAR(diskPAddr);
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UNSERIALIZE_SCALAR(diskBlock);
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UNSERIALIZE_SCALAR(diskOperation);
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UNSERIALIZE_SCALAR(outputChar);
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UNSERIALIZE_SCALAR(inputChar);
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UNSERIALIZE_SCALAR(bootStrapImpure);
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UNSERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaConsole::serialize(ostream &os)
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{
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alphaAccess->serialize(os);
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}
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void
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AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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alphaAccess->unserialize(cp, section);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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SimObjectParam<SimConsole *> sim_console;
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SimObjectParam<SimpleDisk *> disk;
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Param<int> num_cpus;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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SimObjectParam<System *> system;
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SimObjectParam<BaseCPU *> cpu;
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SimObjectParam<Platform *> platform;
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SimObjectParam<Bus*> io_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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INIT_PARAM(sim_console, "The Simulator Console"),
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INIT_PARAM(disk, "Simple Disk"),
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INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu, "Processor"),
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INIT_PARAM(platform, "platform"),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
|
|
|
|
CREATE_SIM_OBJECT(AlphaConsole)
|
|
{
|
|
return new AlphaConsole(getInstanceName(), sim_console, disk,
|
|
system, cpu, platform, num_cpus, mmu,
|
|
addr, hier, io_bus);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
|